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ATAR862-4_06资料

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Features

•Single Package Fully-integrated ROM Mask 4-bit Microcontroller with RF Transmitter•Low Power Consumption in Sleep Mode (<1µA Typically)

•Maximum Output Power (10dBm) with Low Supply Current (9.5mA Typically)•2.0V to 4.0V Operation Voltage for Single Li-cell Power Supply•-40°C to +125°C Operation Temperature•SSO24 Package

•About Seven External Components

•

Flash Controller for Application Program Available

1.Description

The ATAR862-4 is a single package triple-chip circuit. It combines a UHF ASK/FSKtransmitter with a 4-bit microcontroller and a 512-bit EEPROM. It supports highlyintegrated solutions in car access and tire pressure monitoring applications, as well asmanifold applications in the industrial and consumer segment. It is available for thetransmitting frequency range of 429MHz to 439MHz with data rates up to 32kbaudManchester coded.

For further frequency ranges such as 310MHz to 330MHz and 868MHz to 928MHzseparate datasheets are available.

The device contains a ROM mask version microcontroller and an additional dataEEPROM.

Figure 1-1.Application Diagram

ATAR862-4AntennaMicro-PLL-UHF ASK/FSKKeyscontrollerTransmitterReceiverMicro-controllerMicrocontroller with UHF ASK/FSK TransmitterATAR862-4 4552G–4BMCU–09/062.Pin Configuration

Figure 2-1.

Pinning SSO24

XTALVSGNDENABLENRESETBP63/T3IBP20/NTEBP23BP41/T2I/VMIBP42/T2OBP43/SD/INT3VSS123456789101112242322212019181716151413ANT1ANT2PA_ENABLECLKBP60/T3OOSC2OSC1BP50/INT6BP52/INT1BP53/INT1BP40/SC/INT3VDDTable 2-1.PinPin Description: RF Part SymbolFunctionConfigurationVS1.5k1.2kVS1XTALConnection for crystalXTAL182 µA234VSGNDENABLESupply voltageGroundEnable inputESD protection circuitry (see Figure 7-5 on page 11)ESD protection circuitry (see Figure 7-5 on page 11)ENABLE200k2

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

Table 2-1.PinPin Description: RF Part (Continued) SymbolFunctionConfigurationVS21CLKClock output signal for microcontroller,the clock output frequency is set by the crystal to fXTAL/4100100CLKPA_ENABLE50kUref=1.1V22PA_ENABLESwitches on power amplifier, used for ASK modulation20 µAANT12324ANT2ANT1Emitter of antenna output stageOpen collector antenna outputANT2Table 2-2.

NameVDD VSSBP20BP40BP41BP42BP43BP50BP52BP53BP60BP63OSC1OSC2NRESET

Pin Description: Microcontroller Part

Type––I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OIOI/O

FunctionSupply voltageCircuit ground

Bi-directional I/O line of Port 2.0Bi-directional I/O line of Port 4.0Bi-directional I/O line of Port 4.1Bi-directional I/O line of Port 4.2Bi-directional I/O line of Port 4.3Bi-directional I/O line of Port 5.0Bi-directional I/O line of Port 5.2Bi-directional I/O line of Port 5.3Bi-directional I/O line of Port 6.0Bi-directional I/O line of Port 6.3Oscillator inputOscillator outputBi-directional reset pin

Alternate Function––

NTE-test mode enable, see section “Master Reset” on page 23

SC-serial clock or INT3 external interrupt inputVMI voltage monitor input or T2I external clock input Timer 2

T2O Timer 2 output

SD serial data I/O or INT3-external interrupt inputINT6 external interrupt inputINT1 external interrupt inputINT1 external interrupt inputT3O Timer 3 outputT3I Timer 3 input

4-MHz crystal input or 32-kHz crystal input or external clock input or external trimming resistor input

4-MHz crystal output or 32-kHz crystal output or external clock input–

Pin No.13127149101117161520618195

Reset State

NANAInputInputInputInputInputInputInputInputInputInputInputInputI/O

4552G–4BMCU–09/06

3.UHF ASK/FSK Transmitter Block4.Features

•Integrated PLL Loop Filter

•Maximum Output Power (10dBm) with Low Supply Current (9.5mA Typically)•Modulation Scheme ASK/FSK

–FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-drain Output of the Modulating Microcontroller

Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power SupplySupply Voltage 2.0V to 4.0V in the Temperature Range of -40°C to +125°CSingle-ended Antenna Output with High Efficient Power AmplifierExternal CLK Output for Clocking the Microcontroller125°C Operation for Tire Pressure Systems

•••••

5.Description

The PLL transmitter block has been developed for the demands of RF low-cost transmissionsystems, at data rates up to 32kbaud. The transmitting frequency range is 429MHz to439MHz. It can be used in both FSK and ASK systems.

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

Figure 5-1.

Block Diagram

ATAR862-4Power up/ENABLEdownCLKf4f32PFDVSPA_ENABLEGNDCPANT2LFANT1XTALPAVCOXTOPLLOSC2OSC1VDDVSSMicrocontrollerNRESETBrown-out protect.RCCrystalExternalRESEToscillatorsoscillatorsclock inputUTCMTimer 1Voltage monitor External inputClock managementinterval- andwatchdog timerVMITimer 2T2IBP10T2OPort 1ROMRAM8-/12-bit timerwith modulatorBP134 K x 8 bit256 x 4 bitSDSSIBP20/NTESerial interfaceSCnoi4-bit CPU coreTimer 3T3OBP21t2c terr8-bitiBP22oPdtimer/counterT3I ataI/O buswith modulatorBP23Dand demodulatorData direction +Data direction +Data direction +EEPROMalternate functioninterrupt controlalternate functionPort 4Port 5Port 632 x 16 bitBP51INT6BP40BP41BP42BP43BP50BP52BP53BP60BP63INT3 VMI T2OINT3INT6INT1 SCINT1 T3O T3I T2I SD4552G–4BMCU–09/06

6.General Description

The fully-integrated PLL transmitter that allows particularly simple, low-cost RF miniature trans-mitters to be assembled. The VCO is locked to 32×fXTAL, thus, a 13.56MHz crystal is neededfor a 433.92MHz transmitter. All other PLL and VCO peripheral elements are integrated.The XTO is a series resonance oscillator so that only one capacitor together with a crystal con-nected in series to GND are needed as external elements.

The crystal oscillator together with the PLL needs maximum <1ms until the PLL is locked andthe CLK output is stable. A wait time of ≥1ms until the CLK is used for the microcontroller andthe PA is switched on.

The power amplifier is an open-collector output delivering a current pulse which is nearly inde-pendent from the load impedance. The delivered output power is controlled via the connectedload impedance.

This output configuration enables a simple matching to any kind of antenna or to 50Ω. A highpower efficiency of η=Pout/(IS,PA×VS) of 36% for the power amplifier results when an optimizedload impedance of ZLoad=(166+j223)Ω is used at 3V supply voltage.

7.Functional Description

If ENABLE=L and PA_ENABLE=L, the circuit is in standby mode consuming only a very smallamount of current so that a lithium cell used as power supply can work for several years.With ENABLE=H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remainsL, only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller.The VCO locks to 32 times the XTO frequency.

With ENABLE=H and PA_ENABLE=H, the PLL, XTO, CLK driver and the power amplifier areon. With PA_ENABLE, the power amplifier can be switched on and off, which is used to performthe ASK modulation.

7.1ASK Transmission

The PLL transmitter block is activated by ENABLE=H. PA_ENABLE must remain L for t≥1ms,then the CLK signal can be taken to clock the microcontroller and the output power can be mod-ulated by means of pin PA_ENABLE. After transmission, PA_ENABLE is switched to L and themicrocontroller switches back to internal clocking. The PLL transmitter block is switched back tostandby mode with ENABLE=L.

7.2FSK Transmission

The PLL transmitter block is activated by ENABLE=H. PA_ENABLE must remain L for t≥1ms,then the CLK signal can be taken to clock the microcontroller and the power amplifier is switchedon with PA_ENABLE=H. The chip is then ready for FSK modulation. The microcontroller startsto switch on and off the capacitor between the XTAL load capacitor and GND with an open-drainoutput port, thus changing the reference frequency of the PLL. If the switch is closed, the outputfrequency is lower than if the switch is open. After transmission PA_ENABLE is switched to Land the microcontroller switches back to internal clocking. The PLL transmitter block is switchedback to standby mode with ENABLE=L.

The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol-lowing tolerances are considered.

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

Figure 7-1.

Tolerances of Frequency Modulation

~VSXTALCStray1CMLMC0Crystal equivalent circuitCStray2RSC5CSwitchC4Using C4=9.2pF ±2%, C5=6.8pF ±5%, a switch port with CSwitch=3pF ±10%, stray capaci-tances on each side of the crystal of CStray1=CStray2=1pF ±10%, a parallel capacitance of thecrystal of C0=3.2pF ±10% and a crystal with CM=13fF ±10%, an FSK deviation of ±21kHztypical with worst case tolerances of ±16.3kHz to ±28.8kHz results.

~7.3CLK Output

An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOScompatible if the load capacitance is lower than 10pF.

7.3.1

Clock Pulse Take Over

The clock of the crystal oscillator can be used for clocking the microcontroller. The microcontrol-ler block has the special feature of starting with an integrated RC-oscillator to switch on the PLLtransmitter block with ENABLE=H, and after 1ms to assume the clock signal of the transmis-sion IC, so the message can be sent with crystal accuracy.Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power isachieved with a load impedance of ZLoad,opt=(166+j223)Ω. There must be a low resistive pathto VS to deliver the DC current.

The delivered current pulse of the power amplifier is 9mA and the maximum output power isdelivered to a resistive load of 465Ω if the 1.0pF output capacitance of the power amplifier iscompensated by the load impedance.

An optimum load impedance of:

ZLoad=465Ω||j/(2×π1.0pF)=(166+j223)Ω thus results for the maximum output power of7.5dBm.

The load impedance is defined as the impedance seen from the PLL transmitter block’s ANT1,ANT2 into the matching network. Do not confuse this large signal load impedance with a smallsignal input impedance delivered as input characteristic of RF amplifiers and measured from theapplication into the IC instead of from the IC into the application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 465Ω where the parallelimaginary part should be kept constant.

Output power measurement can be done with the circuit shown in Figure 7-2 on page 8. Notethat the component values must be changed to compensate the individual board parasitics untilthe PLL transmitter block has the right load impedance ZLoad,opt=(166+j223)Ω. Also the damp-ing of the cable used to measure the output power must be calibrated.

7.3.2

4552G–4BMCU–09/06

Figure 7-2.Output Power Measurement

VSC1 = 1nL1 = 33nANT1ZLoptANT2~C2 = 2.2p~PowermeterZ = 50 ΩRin50 Ω7.4Application Circuit

For the supply-voltage blocking capacitor C3, a value of 68nF/X7R is recommended (see Figure7-3 on page 9 and Figure 7-4 on page 10). C1 and C2 are used to match the loop antenna to thepower amplifier where C1 typically is 8.2pF/NP0 and C2 is 6pF/NP0 (10pF+15pF in series);for C2 two capacitors in series should be used to achieve a better tolerance value and to havethe possibility to realize the ZLoad,opt by using standard valued capacitors.

C1 forms together with the pins of PLL transmitter block and the PCB board wires a series reso-nance loop that suppresses the 1st harmonic, thus, the position of C1 on the PCB is important.Normally the best suppression is achieved when C1 is placed as close as possible to the pinsANT1 and ANT2.

The loop antenna should not exceed a width of 1.5mm, otherwise the Q-factor of the loopantenna is too high.

L1 (≈50nH to 100nH) can be printed on PCB. C4 should be selected so the XTO runs on theload resonance frequency of the crystal. Normally, a value of 12pF results for a 15pFload-capacitance crystal.

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

Figure 7-3.

ASK Application Circuit

VSL1C4XTAL1XTOVCOPA24XTALANT1C1LoopVSLFAntennaVSC2223ANT2CPC3GNDPFD322PA_ENABLE32PLLfENABLE44f21CLKPower up/downNRESETBP60/T3O520BP63/T3I619OSC2BP20/NTE718OSC1BP23BP50/INT6817S1BP41/T2I/VMIBP52/INT1916S2BP42/T2OBP53/INT11015S3BP43/SD/INT3BP40/SC/INT31117VSS12VDD13VS4552G–4BMCU–09/06

Figure 7-4.FSK Application Circuit

VSL1C4C5XTALXTAL1XTOVCOPA24ANT1C1VSVS2CPC323ANT2LFC2LoopAntennaGND3PFD22PA_ENABLE32PLLf4fPower up/down21ENABLE4CLKNRESET5BP63/T3I6BP20/NTE7BP238BP41/T2I/VMI9BP42/T2O10BP43/SD/INT311VSS12BP60/T3O20OSC219OSC118BP50/INT6S117BP52/INT1S216BP53/INT1S315BP40/SC/INT317VDD13VS10

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

Figure 7-5.

ESD Protection Circuit

VSANT1CLKPA_ENABLEANT2XTALENABLEGND8.Absolute Maximum Ratings: RF Part

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ParametersSupply voltagePower dissipationJunction temperatureStorage temperatureAmbient temperatureInput voltageNote:

SymbolVSPtotTjTstgTambVmaxPA_ENABLE

-55-55-0.3Min.

Max.5100150+125+125(VS + 0.3)(1)

UnitVmW°C°C°CV

1.If VS + 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3.7 V.

9.Thermal Resistance

ParametersJunction ambient

SymbolRthJA

Value135

UnitK/W

10.Electrical Characteristics

VS = 2.0V to 4.0V, Tamb = -40°C to +125°C unless otherwise specified.

Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (Pin 3).

Parameters

Test Conditions

Power down,

VENABLE<0.25V, -40°C to +85°CVPA-ENABLE<0.25V, -85°C to +125°CVPA-ENABLE<0.25V, +25°C (100% correlation tested)

Power up, PA off, VS= 3V

VENABLE>1.7V, VPA-ENABLE<0.25VPower up, VS= 3.0V

VENABLE>1.7V, VPA-ENABLE>1.7VVS=3.0V,Tamb=25°C

f = 433.92 MHz, ZLoad = (166 + j233) Ω

Symbol

Min.

Typ.

Max.3507

<103.79

5.5

7.5

4.811.610

UnitnAµAnAmAmAdBm

Supply current

IS_Off

Supply currentSupply currentOutput power

ISIS_TransmitPRef

4552G–4BMCU–09/06

10.Electrical Characteristics (Continued)

VS = 2.0V to 4.0V, Tamb = -40°C to +125°C unless otherwise specified.

Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (Pin 3).

Parameters

Output power variation for the full temperature range

Achievable output-power range

Test ConditionsTamb = -40°C to +85°CVS = 3.0VVS = 2.0V

Tamb = -40°C to +125°CVS = 3.0VVS = 2.0V

POut = PRef + ∆PRef

Selectable by load impedancefCLK = f0/128

Load capacitance at pin CLK = 10pFfO ± 1 ×fCLK fO ± 4 ×fCLK

other spurious are lower

fXTO = f0/32

fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF, load capacitance selected accordingly Tamb = -40°C to +85°CTamb = -40°C to +125°CReferred to fPC = fXT0,

25 kHz distance to carrier25 kHz distance to carrierat 1MHzat 36MHz

fVCO

429

f0/128

CLoad ≤ 10pF

V0h

V0lRs

Duty cycle of the modulation signal = 50%

Low level input voltageHigh level input voltageInput current highLow level input voltageHigh level input voltageInput current high

VIlVIhIInVIlVIhIIn

VS×0.8

VS×0.21107

001.7

1.7

0.25VS(1)532320.25

Symbol∆PRef∆PRef∆PRef∆PRefPOut_typ

0Min.

Typ.

Max.-1.5-4.0-2.0-4.57.5

UnitdBdBdBdBdBm

Spurious emission

-55-52dBcdBc

Oscillator frequency XTO

(= phase comparator frequency)

fXTO

-30-40

fXTAL250-116-86-94-125

-110-80-90-121439+30+40

ppmppmkHzdBc/HzdBc/HzdBc/HzdBc/HzMHzMHzVVΩpFkHzkHzVVµAVVµA

PLL loop bandwidthPhase noise of phase comparator

In loop phase noise PLLPhase noise VCOFrequency range of VCOClock output frequency (CMOS microcontroller compatible)Voltage swing at pin CLKSeries resonance R of the crystalCapacitive load at pin XT0FSK modulation frequency rateASK modulation frequency rateENABLE input

PA_ENABLE inputNote:

1.If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

11.Microcontroller Block12.Features

•••••

Extended Temperature Range for High Temperature up to 125°C4-Kbyte ROM, 256 × 4-bit RAM11 Bi-directional I/Os

Up to Seven External/Internal Interrupt SourcesMultifunction Timer/Counter

–IR Remote Control Carrier Generator

–Biphase-, Manchester- and Pulse-width Modulator and Demodulator–Phase Control Function

Programmable System Clock with Prescaler and Five Different Clock SourcesSupply-voltage Range (2.0 V to 4.0 V)Very Low Sleep Current (< 1µA)32 × 16-bit EEPROM

Synchronous Serial Interface (2-wire, 3-wire)Watchdog, POR and Brown-out FunctionVoltage Monitoring Inclusive Lo_BAT DetectFlash Controller ATAM862 Available (SSO24)

••••••••

13.Description

The ATAR862-4 is a member of Atmel’s family of 4-bit single-chip microcontrollers. TheATAR862-4 is suitable for the transmitter side as well as the receiver side. It contains ROM,RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters with modulator anddemodulator function, voltage supervisor, interval timer with watchdog function and a sophisti-cated on-chip clock generation with external clock input, integrated RC-oscillator, 32-kHz and4-MHz crystal-oscillators. The ATAR862-4 has an EEPROM as a third chip in one package.

4552G–4BMCU–09/06

Figure 13-1.Block Diagram

VSSVDDOSC1OSC2Brown-out protect.RESETVoltage monitor External inputVMIBP10BP13BP20/NTEPort 2RCCrystaloscillatorsoscillatorsExternalclock inputUTCMTimer 1interval- andwatchdog timerTimer 2T2IT2OSDSCT3OT3IClock managementPort 1ROM4 K x 8 bitRAM256 x 4 bit8/12-bit timerwith modulatorSSIMARC4Data directionSerial interfaceTimer 38-bittimer / counterwith modulatorand demodulatorBP21BP22BP234-bit CPU coreI/O busData direction +alternate functionPort 4Data direction +interrupt controlPort 5Data direction +alternate functionPort 6BP40BP42BP50BP52INT3 T2OINT6INT1 SCBP41BP43BP51BP53 VMIINT3INT6INT1 T2I SDBP60 T3OBP63 T3I14.Introduction

The ATAR862-4 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It containsROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters, voltagesupervisor, interval timer with watchdog function and a sophisticated on-chip clock generationwith integrated RC-, 32-kHz and 4-MHz crystal oscillators.Table 14-1.

VersionFlash deviceProduction

Available Variants

TypeATAM862ATAR862

ROM

4-Kbyte EEPROM4-Kbyte Mask ROM

E2PROM Peripheral64-bytes64-bytes

PackagesSSO24SSO24

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

15.MARC4 Architecture General Description

The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chipperipherals. The CPU is based on the Harvard architecture with physically separated programmemory (ROM) and data memory (RAM). Three independent buses, the instruction bus, thememory bus and the I/O bus, are used for parallel communication between ROM, RAM andperipherals. This enhances program execution speed by allowing both instruction prefetching,and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerfulintegrated interrupt controller with associated eight prioritized interrupt levels supports fast andefficient processing of hardware events. The MARC4 is designed for the high-level programminglanguage qFORTH. The core includes both an expression and a return stack. This architectureenables high-level language programming without any loss of efficiency or code density.Figure 15-1.MARC4 Core

MARC4 COREResetProgrammemoryPCXYSPRPRAM256 x 4-bitResetClockInstruction busInstruction decoderMemory busTOSCCRALUSystem clockSleep InterruptcontrollerI/O busOn-chip peripheral modules16.Components of MARC4 Core

The core contains ROM, RAM, ALU, program counter, RAM address registers, instructiondecoder and interrupt controller. The following sections describe each functional block in moredetail.

4552G–4BMCU–09/06

16.1ROM

The program memory (ROM) is mask programmed with the customer application program dur-ing the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide programcounter, thus predefining a maximum program bank size of 4 Kbytes. An additional 1-Kbyte ofROM exists, which is reserved for quality control self-test software The lowest user ROMaddress segment is taken up by a 512-bytes Zero page which contains predefined startaddresses for interrupt service routines and special subroutines accessible with single byteinstructions (SCALL).

The corresponding memory map is shown in Figure 16-1. Look-up tables of constants can alsobe held in ROM and are accessed via the MARC4’s built-in table instruction.Figure 16-1.ROM Map of the Microcontroller Block

FFFh1F8h1F0h1E8h1E0h1E0h1C0h180hINT7INT6INT5INT4INT3INT2INT1INT0SCALL addressesROM(4 K x 8 bit)7FFhZeropage140h100h0C0h080h1FFh000hZero page020h018h010h008h000h040h008h000h$RESET$AUTOSLEEP16.2RAM

The microcontroller block contains 256×4-bit wide static random access memory (RAM), whichis used for the expression stack. The return stack and data memory are used for variables andarrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, Xand Y.

16.2.1

Expression Stack

The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arith-metic, I/O and memory reference operations take their operands, and return their results to theexpression stack. The MARC4 performs the operations with the top of stack items (TOS andTOS-1). The TOS register contains the top element of the expression stack and works in thesame way as an accumulator. This stack is also used for passing parameters between subrou-tines and as a scratch pad area for temporary storage of data.Return Stack

The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storingreturn addresses of subroutines, interrupt routines and for keeping loop index counts. The returnstack can also be used as a temporary storage area.

The MARC4 instruction set supports the exchange of data between the top elements of theexpression stack and the return stack. The two stacks within the RAM have a user definablelocation and maximum depth.

16.2.2

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

Figure 16-2.RAM Map

(256 x 4-bit)AutosleepFChFFhGlobalvariables RAMExpression stack30TOSTOS-1TOS-24-bitExpressionstackReturnstackSPRAM address register:XYSPRP04h00h07h03hReturn stack110RPTOS-1Globalvvariables12-bit16.3Registers

The microcontroller has seven programmable registers and one condition code register (see

Figure 16-3).

16.3.1

Program Counter (PC)

The program counter is a 12-bit register which contains the address of the next instruction to befetched from the ROM. Instructions currently being executed are decoded in the instructiondecoder to determine the internal micro-operations. For linear code (no calls or branches), theprogram counter is incremented with every instruction cycle. If a branch-, call-, return-instructionor an interrupt is executed, the program counter is loaded with a new address. The programcounter is also used with the table instruction to fetch 8-bit wide ROM constants.

Figure 16-3.Programming Mode l

11PC7RP7SP7X7Y3TOSCCR3C--B0I0Top of stack registerCondition code registerInterrupt enableBranchReservedCarry / borrow0RAM address register (Y)0RAM address register (X)0000Expression stack pointerReturn stack pointer0Program counter17

4552G–4BMCU–09/06

16.3.2

RAM Address Registers

The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. Theseregisters allow access to any of the 256 RAM nibbles.Expression Stack Pointer (SP)

The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expressionstack. The pointer is automatically pre-incremented if a nibble is moved onto the stack orpost-decremented if a nibble is removed from the stack. Every post-decrement operation movesthe item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stackpointer has to be initialized with >SPS0 to allocate the start address of the expression stackarea.Return Stack Pointer (RP)

The return stack pointer points to the top element of the 12-bit wide return stack. The pointerautomatically pre-increments if an element is moved onto the stack, or it post-decrements if anelement is removed from the stack. The return stack pointer increments and decrements insteps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is leftunwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a resetthe return stack pointer has to be initialized via >RPFCh.RAM Address Registers (Xand Y)

The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation movesthe addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAMlocation. By using either the pre-increment or post-decrement addressing mode arrays in theRAM can be compared, filled or moved.Top of Stack (TOS)

The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory refer-ence and I/O operations use this register. The TOS register receives data from the ALU, ROM,RAM or I/O bus.Condition Code Register (CCR)

The 4-bit wide condition code register contains the branch, the carry and the interrupt enableflag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALUoperations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of thecondition code register.Carry/Borrow (C)

The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit (ALU)occurred during the last arithmetic operation. During shift and rotate operations, this bit is usedas a fifth bit. Boolean operations have no effect on the C-flag.Branch (B)

The branch flag controls the conditional program branching. Should the branch flag has been setby a previous instruction, a conditional branch will cause a jump. This flag is affected by arith-metic, logic, shift, and rotate operations.

16.3.3

16.3.4

16.3.5

16.3.6

16.3.7

16.3.8

16.3.9

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

16.3.10

Interrupt Enable (I)

The interrupt enable flag globally enables or disables the triggering of all interrupt routines withthe exception of the non-maskable reset. After a reset or while executing the DI instruction, theinterrupt enable flag is reset, thus disabling all interrupts. The core will not accept any furtherinterrupt requests until the interrupt enable flag has been set again by either executing an EI orSLEEP instruction.

16.4ALU

The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele-ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALUoperations affects the carry/borrow and branch flag in the condition code register (CCR).Figure 16-4.ALU Zero-address Operations

RAMSPTOS-1TOS-2TOS-3TOS-4ALUCCRTOS16.5I/O Bus

The I/O ports and the registers of the peripheral modules are I/O mapped. All communicationbetween the core and the on-chip peripherals take place via the I/O bus and the associated I/Ocontrol. With the MARC4 IN and OUT instructions, the I/O bus allows a direct read or writeaccess to one of the 16 primary I/O addresses. More about the I/O access to the on-chip periph-erals is described in the section “Peripheral Modules” on page 32. The I/O bus is internal and isnot accessible by the customer on the final microcontroller device, but it is used as the interfacefor the MARC4 emulation (see section “Emulation” on page 105).

16.6Instruction Set

The MARC4 instruction set is optimized for the high level programming language qFORTH.Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast andcompact program code. The CPU has an instruction pipeline allowing the controller to prefetchan instruction from ROM at the same time as the present instruction is being executed. TheMARC4 is a zero-address machine, the instructions contain only the operation to be performedand no source or destination address fields. The operations are implicitly performed on the dataplaced on the stack. There are one- and two-byte instructions which are executed within 1 to 4machine cycles. A MARC4 machine cycle is made up of two system clock cycles(SYSCL). Mostof the instructions are only one byte long and are executed in a single machine cycle. For moreinformation refer to the “MARC4 Programmer’s Guide”.

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16.7Interrupt Structure

The MARC4 can handle interrupts with eight different priority levels. They can be generatedfrom the internal and external interrupt sources or by a software interrupt from the CPU itself.Each interrupt level has a hard-wired priority and an associated vector for the service routine inthe ROM (see Table 16-1 on page 21). The programmer can postpone the processing of inter-rupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still beregistered, but the interrupt routine only started after the I-flag is set. All interrupts can bemasked, and the priority individually software configured by programming the appropriate controlregister of the interrupting module (see section “Peripheral Modules” on page 32).

16.7.1

Interrupt Processing

For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples allinterrupt requests during every non-I/O instruction cycle and latches these in the interrupt pend-ing register. If no higher priority interrupt is present in the interrupt active register, it signals theCPU to interrupt the current program execution. If the interrupt enable bit is set, the processorenters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to theservice routine is executed and the current PC is saved on the return stack. An interrupt serviceroutine is completed with the RTI instruction. This instruction resets the corresponding bits in theinterrupt pending/active register and fetches the return address from the return stack to the pro-gram counter. When the interrupt enable flag is reset (triggering of interrupt routines is disabled),the execution of new interrupt service routines is inhibited but not the logging of the interruptrequests in the interrupt pending register. The execution of the interrupt is delayed until the inter-rupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs whilethe corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yetfinished).

It should be noted that automatic stacking of the RBR is not carried out by the hardware and soif ROM banking is used, the RBR must be stacked on the expression stack by the applicationprogram and restored before the RTI. After a master reset (power-on, brown-out or watchdogreset), the interrupt enable flag and the interrupt pending and interrupt active register are allreset.

16.7.2

Interrupt Latency

The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou-tine being activated. This is extremely short (taking between 3 to 5 machine cycles dependingon the state of the core).

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Figure 16-5.Interrupt Handling

INT7765INT5INT7 activeRTIINT5 activePriority level43210INT3INT2INT3 activeRTIRTIINT2 pendingINT2 activeRTISWI0INT0 pendingINT0 activeRTIMain /AutosleepMain /AutosleepTimeTable 16-1.

InterruptINT0INT1INT2INT3INT4INT5INT6INT7

Interrupt Priority Table

PriorityLowest|||||| Highest

ROM Address

040h080h0C0h100h140h180h1C0h1E0h

Interrupt OpcodeC8h (SCALL 040h)D0h (SCALL 080h)D8h (SCALL 0C0h)E8h (SCALL 100h)E8h (SCALL 140h)F0h (SCALL 180h)F8h (SCALL 1C0h)FCh (SCALL 1E0h)

Function

Software interrupt (SWI0)

External hardware interrupt, any edge at BP52 or BP53

Timer 1 interrupt

SSI interrupt or external hardware interrupt at BP40 or BP43Timer 2 interruptTimer 3 interrupt

External hardware interrupt, at any edge at BP50 or BP51

Voltage monitor (VM) interrupt

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Table 16-2.

InterruptINT1INT2INT3INT4INT5INT6INT7

Hardware Interrupts

Interrupt Mask

RegisterP5CRT1MSISCT2CMT3CM1T3CM2T3CP5CRVCM

BitP52M1, P52M2P53M1, P53M2

T1IMSIMT2IMT3IM1T3IM2T3EIMP50M1, P50M2P51M1, P51M2

VIM

Interrupt SourceAny edge at BP52any edge at BP53Timer 1

SSI buffer full/empty or BP40/BP43 interruptTimer 2 compare match/overflowTimer 3 compare register 1 matchTimer 3 compare register 2 matchTimer 3 edge event occurs (T3I)Any edge at BP50,any edge at BP51

External/internal voltage monitoring

16.8Software Interrupts

The programmer can generate interrupts by using the software interrupt instruction (SWI), whichis supported in qFORTH by predefined macros named SWI0...SWI7. The software triggeredinterrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes thetop two elements from the expression stack and writes the corresponding bits via the I/O bus tothe interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior-itized or lower priority processes scheduled for later execution.

16.9Hardware Interrupts

In the microcontroller block, there are eleven hardware interrupt sources with seven different lev-els. Each source can be masked individually by mask bits in the correspondingcontrolregisters. An overview of the possible hardware configurations is shown in Table 16-2.

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17.Master Reset

The master reset forces the CPU into a well-defined condition. It is unmaskable and isactivatedindependent of the current program state. It can be triggered by either initialsupply power-up, ashort collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an exter-nal input clock supervisor stage (see Figure 17-1). A master reset activation will reset theinterrupt enable flag, the interrupt pending register and the interrupt active register. During thepower-on reset phase, the I/O bus control signals are set to reset mode, thereby, initializing allon-chip peripherals. All bi-directional ports are set to input mode.

Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an additionalinternal strong pull-up transistor. This pin must not be pulled down to VSS during reset by anyexternal circuitry representing a resistor of less than 150kΩ.

Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h.This activates the initialization routine $RESET which in turn has to initialize all necessary RAMvariables, stack pointers and peripheral configuration registers (see Table 21-1 on page 34).Figure 17-1.Reset Configuration

VDDPull-upCLNRSTResettimerresCL=SYSCL/4Power-onresetBrown-outdetectionWatch-dogresExt. clocksupervisorVDDVSSVDDInternalresetVSSCWDExIn17.1Power-on Reset and Brown-out Detection

The microcontroller block has a fully integrated power-on reset and brown-out detection circuitry.For reset generation no external components are needed.

These circuits ensure that the core is held in the reset state until the minimum operating supplyvoltage has been reached. A reset condition will also be generated should the supply voltagedrop momentarily below the minimum operating level except when a power-down mode is acti-vated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-downmode the brown-out detection is disabled.

Two values for the brown-out voltage threshold are programmable via the BOTbit in theSCregister.

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A power-on reset pulse is generated by a VDD rise across the default BOT voltage level (1.7 V).A brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Twovalues for the brown-out voltage threshold are programmable via the BOT bit in the SC register.When the controller runs in the upper supply voltage range with a high system clock frequency,the high threshold must be used. When it runs with a lower system clock frequency, the lowthreshold and a wider supply voltage range may be chosen. For further details, see the electricalspecification and the SCregister description for BOT programming.Figure 17-2.Brown-out Detection

VDD2.0 V1.7 VtdCPUResetBOT = '1'tdCPUResetBOT = '0't= 1.5 ms (typically)dtdtBOT = 1, low brown-out voltage threshold 1.7 V (is reset value).BOT = 0, high brown-out voltage threshold 2.0 V.17.1.1

Watchdog Reset

The watchdog’s function can be enabled at the WDC register and triggers a reset with everywatchdog counter overflow. To suppress the watchdog reset, the watchdog counter must beregularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly thesame manner as a reset stimulus from any of the above sources.External Clock Supervisor

The external input clock supervisor function can be enabled if the external input clock is selectedwithin the CM and SC registers of the clock module. The CPU reacts in exactly the same man-ner as a reset stimulus from any of the above sources.

17.1.2

18.Voltage Monitor

The voltage monitor consists of a comparator with internal voltage reference. It is used to super-vise the supply voltage or an external voltage at the VMI pin. The comparator for the supplyvoltage has three internal programmable thresholds one lower threshold (2.2V), one middlethreshold (2.6V) and one higher threshold (3.0V). For external voltages at the VMI pin, thecomparator threshold is set to VBG = 1.3V. The VMS bit indicates if the supervised voltage isbelow (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when theVMS bit is set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) isenabled when the interrupt mask bit (VIM) is reset in the VMC register.

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Figure 18-1.Voltage Monitor

VDDVoltage monitorBP41/VMIINOUTINT7VMC :VM2VM1VM0VIMVMST : - - resVMS18.0.1Voltage Monitor Control/ Status Register

Primary register address: \"F’hex\"

Bit 3

VMC: Write

VM2

Bit 2VM1

Bit 1VM0

Bit 0VIM

Reset value: 1111b

VMST: Read––ReservedVMSReset value: xx11b

VM2:VM1:VM0:Table 18-1.

VM211110000

11001100

Voltage monitor Mode bit 2Voltage monitor Mode bit 1Voltage monitor Mode bit 0Voltage Monitor Modes

VM010101010

Function

Disable voltage monitor

External (VIM input), internal reference threshold (1.3 V), interrupt with negative slopeNot allowed

External (VMI input), internal reference threshold (1.3 V), interrupt with positive slope

Internal (supply voltage), high threshold (3.0 V), interrupt with negative slope

Internal (supply voltage), middle threshold (2.6 V), interrupt with negative slope

Internal (supply voltage), low threshold (2.2 V), interrupt with negative slopeNot allowed

VM1

VIM

Voltage Interrupt Mask bit

VIM = 0, voltage monitor interrupt is enabledVIM = 1, voltage monitor interrupt is disabled

Voltage Monitor Status bit

VMS = 0, the voltage at the comparator input is below VRefVMS = 1, the voltage at the comparator input is above VRef

VMS

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Figure 18-2.Internal Supply Voltage Supervisor VMS = 1VDDLow thresholdMiddle thresholdHigh threshold3.0 V2.6 V2.2 VLow thresholdMiddle thresholdHigh thresholdVMS = 0Figure 18-3.External Input Voltage Supervisor

Internal reference levelVMINegative slopeVMS = 11.3 VVMS = 0Positive slopeInterrupt negative slopetVMS = 0Interrupt positive slopeVMS = 119.Clock Generation

19.1

Clock Module

The microcontroller block contains a clock module with 4 different internal oscillator types: twoRC oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1and OSC2 are the interface to connect a crystal either to the 4-MHz, or to the 32-kHz crystaloscillator. OSC1 can be used as input for external clocks or to connect an external trimmingresistor for the RC-oscillator 2. All necessary circuitry, except the crystal and the trimming resis-tor, is integrated on-chip. One of these oscillator types or an external input clock can be selectedto generate the system clock (SYSCL).

In applications that do not require exact timing, it is possible to use the fully integrated RC-oscil-lator 1 without any external components. The RC-oscillator 1 center frequency tolerance isbetter than ± 50%. The RC-oscillator 2 is a trimmable oscillator whereby the oscillator frequencycan be trimmed with an external resistor attached between OSC1 and VDD. In this configuration,the RC-oscillator 2 frequency can be maintained stable with a tolerance of ±15% over the fulloperating temperature and voltage range.

The clock module is programmable via software with the clock management register (CM) andthe system configuration register (SC). The required oscillator configuration can be selected withthe OS1 bit and the OS0 bit in the SC register. A programmable 4-bit divider stage allows theadjustment of the system clock speed. A special feature of the clock management is that anexternal oscillator may be used and switched on and off via a port pin for the power-down mode.Before the external clock is switched off, the internal RC-oscillator 1 must be selected with theCCS bit and then the SLEEP mode may be activated. In this state an interrupt can wake up thecontroller with the RC-oscillator, and the external oscillator can be activated and selected bysoftware. A synchronization stage avoids too short clock periods if the clock source or the clockspeed is changed.

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If an external input clock is selected, a supervisor circuit monitors the external input and gener-ates a hardware reset if the external clock source fails or drops below 500 kHz for more than1ms.

Figure 19-1.Clock Module

OSC1OscinExt. clockExIn*RC oscillator2RTrimExOutStopRCoscillator 1IN1CinIN2/2/2Divider/2/2SYSCLRCOut2StopStopRCOut1Control4-MHz oscillatorOscinOscoutOSC2Oscout4OutStop32-kHz oscillator*OscinOscout32OutOsc-StopCM:SleepWDLCin/16NSTOPCCSCSS1CSS032 kHzSUBCL*mask optionSC:BOT- - -OS1OS0Table 19-1.

Mode1234

Clock Modes

Clock Source for SYSCL

OS01100

CCS = 1

RC-oscillator 1 (internal)RC-oscillator 1 (internal)RC-oscillator 1 (internal)RC-oscillator 1 (internal)

CCS = 0External input clockRC-oscillator 2 with external trimming resistor

4-MHz oscillator32-kHz oscillator

Clock Source for SUBCL

Cin/16Cin/16Cin/1632 kHz

OS11010

The clock module generates two output clocks. One is the system clock (SYSCL) and the otherthe periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCLcan supply only the peripherals with clocks. The modes for clock sources are programmablewith the OS1 bit and OS0 bit in the SC register and the CCS bit in the CM register.

19.2Oscillator Circuits and External Clock Input Stage

The microcontroller block series consists of four different internal oscillators: two RC-oscillators,one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage.

19.2.1

RC-oscillator 1 Fully Integrated

For timing insensitive applications, it is possible to use the fully integrated RC-oscillator1. Itoperates without any external components and saves additional costs. The RC-oscillator1 cen-ter frequency tolerance is better than ±50% over the full temperature and voltage range. Thebasic center frequency of the RC-oscillator 1 is fO≈3.8MHz. The RC-oscillator 1 is selected bydefault after power-on reset.

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Figure 19-2.RC-oscillator 1

RCoscillator 1RcOut1StopRcOut1Osc-StopControl19.2.2

External Input Clock

The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it meetsthe specified duty cycle, rise and fall times and input levels. Additionally, the external clock stagecontains a supervisory circuit for the input clock. The supervisor function is controlled via theOS1, OS0 bit in the SC register and the CCS bit in the CM register. If the external input clock ismissing for more than 1 ms and CCS = 0 is set in the CM register, the supervisory circuit gener-ates a hardware reset.

Figure 19-3.External Input Clock

Ext. input clockExt.ClockorExt.OSC2ClockClock monitorOSC1ExInStopExOutRcOut1Osc-StopCCSResTable 19-2.

OS111x

Supervisor Function Control Bits

OS0110

CCS01x

Supervisor Reset Output (Res)

EnableDisableDisable

19.2.3

RC-oscillator 2 with External Trimming Resistor

The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency canbe trimmed with an external resistor between OSC1 and VDD. In this configuration, the RC-oscil-lator 2 frequency can be maintained stable with a tolerance of ±10% over the full operatingtemperature and a voltage range VDD from 2.5V to 6.0V.

For example: An output frequency at the RC-oscillator 2 of 2MHz can be obtained by connect-ing a resistor Rext=360kΩ (see Figure 19-4 on page 29).

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Figure 19-4.RC-oscillator 2

VDDRCoscillator 2RTrimRcOut2StopRcOut2Osc-StopRextOSC1OSC219.2.4

4-MHz Oscillator

The microcontroller block 4-MHz oscillator options need a crystal or ceramic resonator con-nected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscillator circuitryis integrated, except the actual crystal, resonator, C3 and C4.

Figure 19-5.4-MHz Crystal Oscillator

OSC1*XTAL4 MHzC1*C2mask optionOscin4Out4-MHzoscillatorOscoutStop4OutOsc-StopOSC2*Figure 19-6.Ceramic Resonator

C3OSC1Oscin*Cer.ResC1*C2mask option4Out4-MHzoscillatorOscoutC4*OSC2Stop4OutOsc-Stop19.2.5

32-kHz Oscillator

Some applications require long-term time keeping or low resolution timing. In this case, anon-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and theSYSCL. In this mode, power consumption is greatly reduced. The 32-kHz crystal oscillator cannot be stopped while the power-down mode is in operation.

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Figure 19-7.32-kHz Crystal Oscillator

OSC1*XTAL32 kHzC1*C2mask optionOscin32Out32-kHzoscillatorOscoutOSC2*32OutNote:

Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to sta-bilize oscillation before the oscillator output is used as system clock. This results in an additional delay of about 4ms for the 4-MHz crystal and about 500ms for the 32-kHz crystal.

19.3Clock Management

The clock management register controls the system clock divider and synchronization stage.Writing to this register triggers the synchronization cycle.

19.3.1Clock Management Register (CM)

Auxiliary register address: \"3\"hex

Bit3

CM:

NSTOP

Bit2CCS

Bit1CSS1

Bit0CSS0

Reset value: 1111b

NSTOP

Not STOP peripheral clock

NSTOP = 0, stops the peripheral clock while the core is in SLEEP modeNSTOP = 1, enables the peripheral clock while the core is in SLEEP modeCore Clock Select

CCS = 1, the internal RC-oscillator 1 generates SYSCL

CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on the setting of OS0 and OS1 in the system configuration registerCore Speed Select 1Core Speed Select 0

CCS

CSS1CSS0

Table 19-3.

CSS10110

Core Speed Select

CSS00101

Divider16842

Note–Reset value

––

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19.3.2

System Configuration Register (SC)

Primary register address: \"3\"hex

Bit3

SC: write

BOT

Bit2–

Bit1OS1

Bit0OS0

Reset value: 1x11b

BOT

Brown-Out Threshold

BOT = 1, low brown-out voltage threshold (1.7 V)BOT = 0, high brown-out voltage threshold (2.0 V)Oscillator Select 1Oscillator Select 0

OS1OS0

Table 19-4.

Mode1234Note:

1010

Oscillator Select

OS01100

Input for SUBCL

Cin/16Cin/16Cin/1632 kHz

Selected Oscillators

RC-oscillator 1 and external input clockRC-oscillator 1 and RC-oscillator 2RC-oscillator 1 and 4-MHz crystal oscillatorRC-oscillator 1 and 32-kHz crystal oscillator

OS1

If bit CCS = 0 in the CM register, the RC-oscillator 1 always stops.

20.Power-down Modes

The sleep mode is a shut-down condition which is used to reduce the average system powerconsumption in applications where the microcontroller is not fully utilized. In this mode, the sys-tem clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction setsthe interrupt enable bit (I) in the condition code register to enable all interrupts and stops thecore. During the sleep mode the peripheral modules remain active and are able to generateinterrupts. The microcontroller exits the sleep mode by carrying out any interrupt or a reset.The sleep mode can only be kept when none of the interrupt pending or active register bits areset. The application of the $AUTOSLEEP routine ensures the correct function of the sleepmode. For standard applications use the $AUTOSLEEP routine to enter the power-down mode.Using the SLEEP instruction instead of the $AUTOSLEEP following an I/O instruction requiresto insert 3 non-I/O instruction cycles (for example NOP NOP NOP) between the IN or OUT com-mand and the SLEEP command.

The total power consumption is directly proportional to the active time of the microcontroller. Fora rough estimation of the expected average system current consumption, the following formulashould be used:

Itotal (VDD, fsyscl) = ISleep + (IDD × tactive/ttotal)IDD depends on VDD and fsyscl

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The microcontroller block has various power-down modes. During the sleep mode the clock forthe MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM), it isprogrammable if the clock for the on-chip peripherals is active or stopped during the sleep mode.If the clock for the core and the peripherals is stopped, the selected oscillator is switched off. Anexception is the 32-kHz oscillator, if it is selected it runs continuously independent of theNSTOP-bit. If the oscillator is stopped or the 32-kHz oscillator is selected, power consumption isextremely low.

Table 20-1.Power-down Modes

CPU CoreRUNSLEEPSLEEP

Osc-Stop(1)

NONOYES

Brown-out FunctionActiveActiveSTOP

RC-oscillator 1RC-oscillator 24-MHz Oscillator

RUNRUNSTOP

32-kHz OscillatorRUNRUNRUN

External Input ClockYESYESSTOP

ModeActivePower-downSLEEPNote:

1. Osc-Stop = SLEEP and NSTOP and WDL

21.Peripheral Modules

21.1

Addressing Peripherals

Accessing the peripheral modules takes place via the I/O bus (see Figure 21-1 on page 33). TheIN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register address-ing scheme has been adopted to enable direct addressing of the primary register. To addressthe auxiliary register, the access must be switched with an auxiliary switching module. Thus, asingle IN (or OUT) to the module address will read (or write into) the module primary register.Accessing the auxiliary register is performed with the same instruction preceded by writing themodule address into the auxiliary switching module. Byte wide registers are accessed by multi-ple IN- (or OUT-) instructions. For more complex peripheral modules, with a larger number ofregisters, extended addressing is used. In this case, a bank of up to 16 subport registers areindirectly addressed with the subport address. The first OUT instruction writes the subportaddress to the subaddress register, the second IN or OUT instruction reads data from or writesdata to the addressed subport.

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Figure 21-1.Example of I/O Addressing

Module ASW(Address Pointer)Module M1Module M2Module M3Subaddress Reg.Bank ofPrimary Reg.Aux. Reg.Auxiliary SwitchModuleSubport Fh1Subport Eh5Primary Reg.Subport 1Subport 0Primary Reg.Primary Reg.2364I/O busto other modulesIndirect Subport AccessDual Register AccessSingle Register Access(Subport Register Write)(Primary Register Write)(Primary Register Write)1 Addr. (SPort) Addr. (M1) OUT3 Prim._Data Addr. (M2) OUT6 Prim._Data Addr.(M3) OUT2 SPort _Data Addr. (M1) OUT(Auxiliary Register Write)(Primary Register Read)(Subport Register Read)4 Addr. (M2) Addr. (ASW) OUT1 Addr. (SPort) Addr. (M1) OUT5 Aux._Data Addr. (M2) OUT6 Addr. (M3) IN2 Addr. (M1) INExample of(Primary Register Read)qFORTH(Subport Register Write Byte)3 Addr. (M2) INprogram code1 Addr. (SPort) Addr. (M1) OUT(Auxiliary Register Read)2 SPort _Data(lo) Addr. (M1) OUT4 Addr. (M2) Addr. (ASW) OUT2 SPort _Data(hi) Addr. (M1) OUT5 Addr. (M2) IN(Subport Register Read Byte)(Auxiliary Register Write Byte)1 Addr. (SPort) Addr. (M1) OUT4 Addr. (M2) Addr. (ASW) OUT2 Addr. (M1) IN (hi)5 Aux._Data (lo) Addr. (M2) OUT2 Addr. (M1) IN (lo)5 Aux._Data (hi) Addr. (M2) OUTAddr.(ASW)= Auxiliary Switch Module addressPrim._Data(hi)= Data to be written into Auxiliary Register (high nibble)Addr.(Mx)= Module Mx addressSPort_Data(lo)= Data to be written into SubPort (low nibble)Addr.(SPort)= Subport addressSPort_Data(hi)= Data to be written into SubPort (high nibble)Prim._Data= Data to be written into Primary RegisterAux._Data= Data to be written into Auxiliary Register(lo)= SPort_Data (low nibble)Prim._Data(lo)= Data to be written into Auxiliary Register (low nibble)(hi)= SPort_Data (high nibble)4552G–4BMCU–09/06

Table 21-1.Peripheral Addresses

Name

Write/Read

Reset Value

Module Type

Port Address

Auxiliary

0123456789AB-F

Auxiliary

01234456-F

CDEF

T3CT3ST––VMCVMST

P1DATP2DATP2CRSCCWDCMP4DATP4CRP5DATP5CRP6DATP6CRT12SUB

Subport address

T2CT2M1T2M2T2CM T2CO1T2CO2––T1C1T1C2WDC–ASWSTBSRBSIC1SISCSIC2T3SUB

Subport address

T3MT3CST3CM1T3CM2T3CO1T3CPT3CO2–––––––

W/RW/RWWRWW/RWW/RWW/RWWWWWWWW––WWW–WWRWW/RWW/RWWWWWRW–WR––WR

1xx1b1111b1111b1x11bxxxxb1111b1111b1111 1111b1111b1111 1111b1xx1b1111b–0000b1111b1111b0000b1111b1111 1111b

––1111bx111b1111b1111bxxxx xxxxbxxxx xxxxb1111b1x11b1111b–1111b1111b0000b0000b1111 1111bxxxx xxxxb1111 1111b

–0000bx000b––1111bxx11b

Port 1 - data register/input dataPort 2 - data register/pin dataPort 2 - control registerSystem configuration register Watchdog reset

Clock management registerPort 4 - data register/pin data Port 4 - control register (byte)Port 5 - data register/pin data Port 5 - control register (byte)Port 6 - data register/pin dataPort 6 - control register (byte)Data to Timer 1/2 subportTimer 2 control registerTimer 2 mode register 1Timer 2 mode register 2Timer 2 compare mode registerTimer 2 compare register 1Timer 2 compare register 2 (byte)ReservedReserved

Timer 1 control register 1Timer 1 control register 2Watchdog control registerAuxiliary/switch registerSerial transmit buffer (byte)Serial receive buffer (byte)Serial interface control register 1Serial interface status/control registerSerial interface control register 2Data to/from Timer 3 subportTimer 3 mode registerTimer 3 clock select register Timer 3 compare mode register 1Timer 3 compare mode register 2Timer 3 compare register 1 (byte)Timer 3 capture register (byte)Timer 3 compare register 2 (byte)Reserved

Timer 3 control registerTimer 3 status registerReservedReserved

Voltage monitor control registerVoltage monitor status register

M3M2M2M3M3M2M2M2M2M2M2M2M1M1M1M1M1M1M1––M1M1M1–ASWM2M2M2M2M2M1M1M1M1M1M1M1M1–M3M3––M3M3

– Reserved34

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22.Bi-directional Ports

With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 andPort 6 have a data width of 2 bits (bit 0 and bit 3). All ports may be used for data input or output.All ports are equipped with Schmitt trigger inputs and a variety of mask options for open-drain,open-source, full-complementary outputs, pull-up and pull-down transistors. All Port Data Regis-ters (PxDAT) are I/O mapped to the primary address register of the respective port address andthe Port Control Register (PxCR), to the corresponding auxiliary register.There are five different directional ports available:Port 1Port 2Port 5Port 4Port 6

2-bit wide bi-directional port with automatic full bus width direction switching.4-bit wide bitwise-programmable I/O port.

4-bit wide bitwise-programmable bi-directional port with optional strong pull-ups and programmable interrupt logic.

4-bit wide bitwise-programmable bi-directional port also provides the I/Ointerface to Timer 2, SSI, voltage monitor input and external interrupt input.2-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 3 and external interrupt input.

22.1Bi-directional Port 1

In Port 1 the data direction register is not independently software programmable, the direction ofthe complete port being switched automatically when an I/O instruction occurs (see Figure 22-1on page 36). The port is switched to output mode via an OUT instruction and to input via an INinstruction. The data written to a port will be stored into the output data latches and appearsimmediately at the port pin following the OUT instruction. After RESET all output latches are setto \"1\" and the port is switched to input mode. An IN instruction reads the condition of the associ-ated pins.

Note:

Care must be taken when switching the bi-directional port from output to input. The capacitive pin loading at this port in conjunction with the high resistance pull-ups may cause the CPU to read the contents of the output data register rather than the external input state. To avoid this, one of the following programming techniques should be used:

Use two IN-instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state. Use an OUT instruction followed by an IN instruction. Via the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up/pull-down configuration. Write a \"1\" for pins with pull-up resistors and a \"0\" for pins with pull-down resistors.

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Figure 22-1.Bi-directional Port 1

VDDI/O Bus*(Data out)DQStaticpull-up*Switchedpull-upP1DATyRReset(Direction)OUTINMaster resetSRQBP1y*VDD**) Mask optionsStaticpull-downNQSwitchedpull-down22.2Bi-directional Port 2

As all other bi-directional ports, this port includes a bitwise programmable Control Register(P2CR), which enables the individual programming of each port bit as input or output. It alsoopens up the possibility of reading the pin condition when in output mode. This is a useful fea-ture for self testing and for serial bus applications.

Port 2, however, has an increased drive capability and an additional low resistancepull-up/-down transistor mask option.

Care should be taken connecting external components to BP20/NTE. During any reset phase,the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. Thispin must not be pulled down (active or passive) to VSS during reset by any external circuitry rep-resenting a resistor of less than 150kΩ. This prevents the circuit from unintended switching totest mode enable through the application circuitry at pin BP20/NTE. Resistors less than 150kΩmight lead to an undefined state of the internal test logic thus disabling the application firmware.To avoid any conflict with the optional internal pull-down transistors, BP20 handles the pull-downoptions in a different way than all other ports. BP20 is the only port that switches off thepull-down transistors during reset.

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Figure 22-2.Bi-directional Port 2

VI/O BusSwitchedpull-upDDStaticPull-up*(Data out)I/O BusDSMaster resetI/O BusQP2DATy**BP2y*VDDDSQP2CRy*Switchedpull-down*StaticPull-down (Direction) Mask options*22.2.1Port 2 Data Register (P2DAT)

Primary register address: \"2\"hex

Bit 3 *P2DAT3

Bit 2P2DAT2

Bit 1P2DAT1

Bit 0P2DAT0

Reset value: 1111b

* Bit 3 -> MSB, Bit 0 -> LSB

22.2.2Port 2 Control Register (P2CR)

Auxiliary register address: \"2\"hex

Bit3P2CR3

Bit2P2CR2

Bit1P2CR1

Bit0P2CR0

Reset value: 1111b

Value: 1111b means all pins in input mode

Table 22-1.

Code

3 2 1 0 x x x 1x x x 0x x 1 xx x 0 xx 1 x xx 0 x x1 x x x0 x x x

Port 2 Control Register

Function

BP20 in input modeBP20 in output modeBP21 in input modeBP21 in output modeBP22 in input modeBP22 in output modeBP23 in input modeBP23 in output mode

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22.3Bi-directional Port 5

As all other bi-directional ports, this port includes a bitwise programmable Control Register(P5CR), which allows the individual programming of each port bit as input or output. It alsoopens up the possibility of reading the pin condition when in output mode. This is a useful fea-ture for self testing and for serial bus applications.

The port pins can also be used as external interrupt inputs (see Figure 22-3 and Figure 22-4).The interrupts (INT1 and INT6) can be masked or independently configured to trigger on eitheredge. The interrupt configuration and port direction is controlled by the Port 5 Control Register(P5CR). An additional low resistance pull-up/-down transistor mask option provides an internalbus pull-up for serial bus applications.

The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address \"5\"hand the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is abyte-wide register and is configured by writing first the low nibble and then the high nibble (seesection “Addressing Peripherals” on page 32).Figure 22-3.Bi-directional Port 5

I/O BusSwitchedpull-upVDD*V(Data out)I/O BusDQP5DATySMaster resetIN enableDD*pull-upStatic*BP5y*VDDStaticPull-down** Mask options*Switchedpull-downFigure 22-4.Port 5 External Interrupts

INT1Data inBP52INT6Data inBidir. PortIN_EnableBidir. PortIN_EnableBP51I/O-busI/O-busData inBP53Data inBidir. PortIN_EnableDecoderDecoderDecoderDecoderBidir. PortIN_EnableBP50P5CR:P53M2P53M1P52M2P52M1P51M2P51M1P50M2P50M138

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22.3.1

Port 5 Data Register (P5DAT)

Primary register address: \"5\"hex

Bit3P5DAT3

Bit2P5DAT2

Bit1P5DAT1

Bit0P5DAT0

Reset value: 1111b

22.3.2Port 5 Control Register (P5CR) Byte Write

Auxiliary register address: \"5\"hex

Bit3

First write cycle

P51M2Bit7

Second write cycle

P53M2

Bit2P51M1Bit6P53M1

Bit1P50M2Bit5P52M2

Bit0P50M1Bit4P52M1

Reset value: 1111bReset value: 1111b

P5xM2, P5xM1 – Port 5x interrupt mode/direction code

Table 22-2.

Code3 2 1 0x x 1 1x x 0 1x x 1 0x x 0 01 1 x x0 1 x x1 0 x x0 0 x x

Port 5 Control Register

Second Write Cycle

Code3 2 1 0

Function

Auxiliary Address: \"5\"hex First Write Cycle

Function

BP50 in input mode – interrupt disabledBP50 in input mode – rising edge interrupt BP50 in input mode – falling edge interruptBP50 in output mode – interrupt disabledBP51 in input mode – interrupt disabled

BP51 in input mode – rising edge interrupt

– falling edge interruptBP51 in input mode

BP51 in output mode – interrupt disabled

x x 1 1BP52 in input mode – interrupt disabledx x 0 1BP52 in input mode – rising edge interrupt

x x 1 0BP52 in input mode – falling edge interrupt

x x 0 01 1 x x0 1 x x 1 0 x x0 0 x x

BP52 in output mode – interrupt disabledBP53 in input mode – interrupt disabledBP53 in input mode – rising edge interruptBP53 in input mode – falling edge interruptBP53 in output mode – interrupt disabled

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22.4Bi-directional Port 4

The bi-directional Port 4 is a bitwise configurable I/O port and provides the external pins for theTimer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly thesame way as bi-directional Port2 (see Figure 22-5). Two additional multiplexes allow data and

port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The

I/O-pins for SC and SD line have an additional mode to generate an SSI-interrupt.

All four Port 4 pins can be individually switched by the P4CR-register. Figure 22-5 shows theinternal interfaces to bi-directional Port 4.Figure 22-5.Bi-directional Port 4 and Port 6

I/O Bus IntxPxMRy VDDStatic*VDDSwitchedpull-up*pull-upPInPOutI/O BusDSMaster resetI/O BusDQPxDATy*BPxy*(Direction)VDDStaticpull-downSQSwitchedpull-down**PxCRyPDir Mask options*22.4.1Port 4 Data Register (P4DAT)

Primary register address: \"4\"hex

Bit3P4DAT3

Bit2P4DAT2

Bit1P4DAT1

Bit0P4DAT0

Reset value: 1111b

22.4.2Port 4 Control Register (P4CR) Byte Write

Auxiliary register address: \"4\"hex

Bit3

First write cycle

P41M2Bit7

Second write cycle

P43M2

Bit2P41M1Bit6P43M1

Bit1P40M2Bit5P42M2

Bit0P40M1Bit4P42M1

Reset value: 1111bReset value: 1111b

P4xM2, P4xM1 – Port 4x interrupt mode/direction code

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Table 22-3.

Port 4 Control Register

Second Write Cycle

Code3 2 1 0x x 1 1x x 1 0x x 0 x1 1 x x1 0 x x0 1 x x0 0 x x–

Function

BP42 in input modeBP42 in output mode

BP42 enable alternate function (T2O for Timer 2)BP43 in input modeBP43 in output mode

BP43 enable alternate function (SD for SSI)

BP43 enable alternate function (falling edge interrupt input for INT3)–

Auxiliary Address: \"4\"hex

First Write CycleCode 3 2 1 0

x x 1 1x x 1 0x x 0 1 x x 0 01 1 x x1 0 x x0 1 x x0 0 x x

Function

BP40 in input modeBP40 in output mode

BP40 enable alternate function (SC for SSI) BP40 enable alternate function (falling edge interrupt input for INT3)BP41 in input modeBP41 in output mode

BP41 enable alternate function (VMI for voltage monitor input)

BP41 enable alternate function (T2I external clock input for Timer2)

22.5Bi-directional Port 6

The bi-directional Port 6 is a bitwise configurable I/O port and provides the external pins for theTimer 3. As a normal port, it performs in exactly the same way as bi-directional Port 6 (see Fig-ure 22-5 on page 40). Two additional multiplexes allow data and port direction control to bepassed over to other internal module (Timer 3). The I/O pin for T3I line has an additional mode togenerate a Timer 3 interrupt.

AlltwoPort 6 pins can be individually switched by the P6CR register. Figure 22-5 on page 40shows the internal interfaces to bi-directional Port 6.

22.5.1Port 6 Data Register (P6DAT)

Primary register address: \"6\"hex

Bit3P6DAT3

Bit2–

Bit1–

Bit0P6DAT0

Reset value: 1xx1b

22.5.2Port 6 Control Register (P6CR)

Auxiliary register address: \"6\"hex

Bit3P63M2

Bit2P63M1

Bit1P60M2

Bit0P60M0

Reset value: 1111b

P6xM2, P6xM1 – Port 6x interrupt mode/direction code

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Table 22-4.

Code3 2 1 0x x 1 1x x 1 0x x 0 x

Port 6 Control Register

Auxiliary Address: \"6\"hex Write Cycle

Function

BP60 in input modeBP60 in output mode

BP60 enable alternate port function (T3O for Timer 3)

Code3 2 1 01 1 x x1 0 x x0 x x x

Function

BP63 in input modeBP63 in output mode

BP63 enable alternate port function (T3I for Timer 3)

22.6Universal Timer/Counter/ Communication Module (UTCM)

The Universal Timer/counter/Communication Module (UTCM) consists of three timers(Timer1,Timer2, Timer3) and a Synchronous Serial Interface (SSI).

•Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for Timer2, Timer3, the serial interface and the watchdog function.•Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).•Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O).

•The SSI operates as two wire serial interface or as shift register for modulation and

demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register.

There is a multitude of modes in which the timers and the serial interface can work together.

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Figure 22-6.UTCM Block Diagram

SYSCLSUBCLfrom clock moduleTimer 1WatchdogMUXInterval / PrescalerNRSTINT2T1OUTTimer 3Capture 3ControlDemodu-lator 3Modu-lator 3INT5T3OT3IMUX8-bit Counter 3Compare 3/1Compare 3/2TOG3MUXTimer 24-bit Counter 2/1Compare 2/1Modu-lator 2I/O busT2OT2IPOUTMUXDCGControl8-bit Counter 2/2INT4Compare 2/2TOG2SSIReceive bufferSCLMUX8-bit shift registerTransmit bufferControlINT3SCSD22.7Timer 1

The Timer 1 is an interval timer which can be used to generate periodical interrupts and as pres-caler for Timer2, Timer3, the serial interface and the watchdog function.

The Timer1 consists of a programmable 14-stage divider that is driven by either SUBCL orSYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source forthe Timer 1 interrupt. Because of other system requirements, the Timer 1 output T1OUT is syn-chronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep andOSC-Stop -> yes), the output T1OUT is stopped (T1OUT=0). Nevertheless, the Timer 1 can beactive in SLEEP and generate Timer1 interrupts. The interrupt is maskable via the T1IM bit andthe SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for thetimer output can be programmed via the Timer1 control register T1C1.

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This timer starts running automatically after any power-on reset! If the watchdog function is notactivated, the timer can be restarted by writing into the T1C1 register with T1RM=1.

Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdogtimer is a 3-bit counter that is supplied by a separate output of Timer1. It generates a systemreset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before itoverflows. The application software has to accomplish this by reading the CWD register.After power-on reset the watchdog must be activated by software in the $RESET initializationroutine. There are two watchdog modes, in one mode the watchdog can be switched on and offby software, in the other mode the watchdog is active and locked. This mode can only bestopped by carrying out a system reset.

The watchdog timer operation mode and the time interval for the watchdog reset can be pro-grammed via the watchdog control register (WDC).

Figure 22-7.Timer 1 Module

SYSCLSUBCLWDCLMUXCL1Prescaler14 bitWatchdog4 bitNRSTINT2T1CST1MUXT1BPT1IMT1OUTFigure 22-8.Timer 1 and Watchdog

T1C1T1RMT1C2T1C1T1C03Write of theT1C1 registerT1C2T1BPT1IMDecoderMUX for interval timerT1MUXT1IM=0INT2T1IM=1T1OUTRESQ1Q2Q3Q4Q5CL1CLQ6Q8Q8Q11Q11Q14SUBCLQ14WatchdogDivider / 8Decoder2WDCWDLWDRWDT1WDT0MUX for watchdog timerWDCLRESDividerRESETRESET(NRST)Watchdogmode controlRead of theCWD register44

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22.7.1

Timer 1 Control Register 1 (T1C1)

Address: \"7\"hex - Subaddress: \"8\"hex

Bit 3 *T1RM

Bit 2T1C2

Bit 1T1C1

Bit 0T1C0

Reset value: 1111b

* Bit 3 -> MSB, Bit 0 -> LSB

Timer 1 Restart Mode T1RM = 0, write access without Timer 1 restart

......T1RM = 1, write access with Timer 1 restart

Note: If WDL = 0, Timer 1 restart is impossibleTimer 1 Control bit 2Timer 1 Control bit 1Timer 1 Control bit 0

T1RMT1C2T1C1T1C0

The three bits T1C[2:0] select the divider for Timer1. The resulting time interval depends on thisdivider and the Timer1 input clock source. The timer input can be supplied by the system clock,the 32-kHz oscillator or via the clock management. If the clock management generates theSUBCL, the selected input clock from the RC oscillator, 4-MHz oscillator or an external clock isdivided by 16.

Table 22-5.

T1C2

T1C1

Timer 1 Control Bits

T1C0

Divider

Time Interval with

SUBCL

Time Interval withSUBCL = 32 kHz

Time Interval with SYSCL = 2/1 MHz

00001111

00110011

01010101

2481632256204816384

SUBCL/2SUBCL/4SUBCL/8SUBCL/16SUBCL/32SUBCL/256SUBCL/2048SUBCL/16384

61 µs122 µs244 µs488 µs0.977 ms7.812 ms62.5 ms500 ms

1 µs/2 µs2 µs/4 µs4 µs/8 µs8 µs/16 µs16 µs/32 µs128 µs/256 µs1024 µs/2048 µs8192 µs/16384 µs

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22.7.2Timer 1 Control Register 2 (T1C2)

Address: \"7\"hex - Subaddress: \"9\"hex

Bit 3 *–

Bit 2T1BP

Bit 1T1CS

Bit 0T1IM

Reset value: x111b

* Bit 3 -> MSB, Bit 0 -> LSB

Timer 1 SUBCL ByPassedT1BP = 1, TIOUT = T1MUXT1BP = 0, T1OUT = SUBCL

Timer 1 input Clock Select

T1CS = 1, CL1 = SUBCL (see Figure 22-7 on page 44)T1CS = 0, CL1 = SYSCL (see Figure 22-7 on page 44)Timer 1 Interrupt Mask

T1IM = 1, disables Timer 1 interruptT1IM = 0, enables Timer 1 interrupt

T1BP

T1CS

T1IM

22.7.3Watchdog Control Register (WDC)

Address: \"7\"hex - Subaddress: \"A\"hex

Bit 3 *WDL

Bit 2WDR

Bit 1WDT1

Bit 0WDT0

Reset value: 1111b

* Bit 3 -> MSB, Bit 0 -> LSB

WatchDog Lock mode

WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit

WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no

effect. After the WDL-bit is cleared, the watchdog is active until asystem reset or power-on reset occurs.WatchDog Run and stop mode

WDR = 1, the watchdog is stopped/disabledWDR = 0, the watchdog is active/enabledWatchDog Time 1WatchDog Time 0

WDL

WDRWDT1WDT0

Both these bits control the time interval for the watchdog reset.

Table 22-6.

WDT10011

Watchdog Time Control Bits

WDT00101

Divider512204816384131072

Delay Time to Reset with

SUBCL = 32 kHz

15.625 ms62.5 ms0.5 s4 s

Delay Time to Reset with

SYSCL = 2/1 MHz

0.256 ms/0.512 ms1.024 ms/2.048 ms8.2 ms/16.4 ms65.5 ms/131 ms

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22.8

Timer 2

8-/12-bit Timer for:

•Interrupt, square-wave, pulse and duty cycle generation•Baud-rate generation for the internal shift register

•Manchester and Biphase modulation together with the SSI•Carrier frequency generation and modulation together with the SSI

Timer 2 can be used as an interval timer for interrupt generation, as signal generator or asbaud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit upcounter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cas-cadable as a 12-bit timer or as an 8-bit timer with 4-bit prescaler. The timer can also beconfigured as an 8-bit timer and a separate 4-bit prescaler.

The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer1 output clock, the Timer 3 output clock or the shift clock of the serial interface. The externalinput clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer2 with ahigher clock speed than SYSCL. Furthermore, with that input clock the Timer2 operates in thepower-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in thePOWER-DOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources supply noclock signal in SLEEP if NSTOP = 0. The 4-bit counter stages of Timer 2 have an additionalclock output (POUT).

Its output has a modulator stage that allows the generation of pulses as well as the generationand modulation of carrier frequencies. The Timer 2 output can modulate with the shift registerdata output to generate Biphase- or Manchester code.

If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a specialtask. The shift register can only handle bitstream lengths divisible by 8. For other lengths, the4-bit counter stage can be used to stop the modulator after the right bitcount is shifted out.If the timer is used for carrier frequency modulation, the 4-bit stage works together with an addi-tional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and dutycycle. The 8-bit counter is used to enable and disable the modulator output for a programmablecount of pulses.

For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For pro-gramming the timer function, it has four mode and control registers. The comparator output ofstage 2 is controlled by a special compare mode register (T2CM). This register contains maskbits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by acompare match event or the counter overflow. This architecture enables the timer function forvarious modes.

The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Boththese compare registers are cascadable as a 12-bit compare register, or 8-bit compare registerand 4-bit compare register.For 12-bit compare data value:For 8-bit compare data value:For 4-bit compare data value:

m = x +1n = y +1l = z +1

0 ≤ x ≤ 40950 ≤ y ≤ 2550 ≤ z ≤ 15

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Figure 22-9.Timer 2 I/O-busP4CRT2IT2M1T2M2SYSCLT1OUTTOG3SCLDCGOCL2/14-bit Counter 2/1RESOVF1POUTCL2/2T2ODCG8-bit Counter 2/2RESOVF2TOG2OUTPUTM2MOUTBiphase-,Manchester-modulatorT2CCompare 2/1CM1ControlCompare 2/2INT4toModulator 3T2CO1SSIPOUTT2CMT2CO2Timer 2modulatoroutput-stageSOI/O-busSSIControlSSI22.9

22.9.1

Timer 2 Modes

Mode 1: 12-bit Compare Counter

The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare matchsignal of the 4-bit and the 8-bit stage generates the signal for the counter reset, toggle flip-flop orinterrupt. The compare action is programmable via the compare mode register (T2CM). The4-bit counter overflow (OVF1) supplies the clock output (POUT) with clocks. The duty cycle gen-erator (DCG) has to be bypassed in this mode.

Figure 22-10.12-bit Compare Counter

POUT (CL2/1 /16)CL2/1OVF2TOG2RESINT4CM2Timer 2output modeand T2OTM-bitT2D1, 04-bit counterRESDCG8-bit counter4-bit compareCM18-bit compare4-bit register8-bit registerT2RMT2OTMT2IMT2CTM48

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22.9.2

Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler

Figure 22-11.8-bit Compare Counter

DCGOPOUTCL2/1OVF2TOG2RESINT4CM2Timer 2output modeand T2OTM-bit4-bit counterRESDCG8-bit counter4-bit compareCM18-bit compare4-bit registerT2D1, 08-bit registerT2RMT2OTMT2IMT2CTMThe 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, aduty cycle stage is also available. This stage can be used as an additional 2-bit prescaler or forgenerating duty cycles of 25%, 33% and 50%. The 4-bit compare output (CM1) supplies theclock output (POUT) with clocks.

22.9.3

Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler

Figure 22-12.4-/8-bit Compare Counter

DCGOT2ISYSCLCL2/2OVF2TOG2DCG8-bit counterRESINT4CM2Timer 2output modeand T2OTM-bitP4CRP41M2, 1T2D1, 08-bit compare8-bit registerT2RMT2OTMT2IMT2CTMTOG3T1OUTSYSCLSCLMUXCL2/14-bit counterRESCM1POUT4-bit compareT2CS1, 04-bit registerIn these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit prescalerand an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in the mode 3 andmode 4, can the 8-bit counter be supplied via the external clock input (T2I) which is selected viathe P4CR register. The 4-bit prescaler is started via activating of mode 3 and stopped and resetin mode 4. Changing mode 3 and 4 has no effect for the 8-bit timer stage. The 4-bit stage can beused as prescaler for Timer 3, the SSI or to generate the stop signal for modulator 2 andmodulator3.

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22.10Timer 2 Output Modes

The signal at the timer output is generated via modulator2. In the toggle mode, the comparematch event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bitscan be used to toggle the output. In the duty cycle burst modulator modes the DCG output isconnected to T2O and switched on and off either by the toggle flip-flop output or the serial dataline of the SSI. Modulator 2 also has two modes to output the content of the serial interface asBiphase or Manchester code.

The modulator output stage can be configured by the output control bits in the T2M2 register.The modulator is started with the start of the shift register (SIR=0) and stopped either by carry-ing out a shift register stop (SIR=1) or compare match event of stage 1 (CM1) of Timer 2. Forthis task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internalshift clock (SCL).

Figure 22-13.Timer 2 Modulator Output Stage

DCGOSOTOG2REBiphase/ManchestermodulatorToggleRES/SETModulator3OMSKT2M2T2OS2, 1, 0T2TOPM2M2S2S3T2OSSICONTROLFES122.11Timer 2 Output Signals

22.11.1

Timer 2 Output Mode 1

Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 22-14.Interrupt Timer/Square Wave Generator – the Output Toggles with Each Edge

Compare Match Event

InputCounter 2T2RCounter 2CMxINT4T2O000123401234012340150

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Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 22-15.Pulse Generator – the Timer Output Toggles with the Timer Start if the T2TSbit

Is Set

InputCounter 2T2RCounter 2CMxINT4T2OToggleby start00012345674095/2550123456T2OToggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 22-16.Pulse Generator – the Timer Toggles with Timer Overflow and Compare Match

InputCounter 2T2RCounter 2CMxOVF2INT4T2O00012345674095/255012345651

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22.11.2Timer 2 Output Mode 2

Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2)

Figure 22-17.Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output

DCGOCounter 2TOG2M2T2OCounter = compare register (=2)1201201234501201234567801234567891001234522.11.3

Timer 2 Output Mode 3

Duty Cycle Burst Generator 2: The DCG output signal (DCGO) is given to the output, and

gated by the SSI internal data output (SO)

Figure 22-18.Carrier Frequency Burst Modulation with the SSI Data Output

DCGOCounter 2TOG2SOT2OBit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8Bit 9Bit 10Bit 11Bit 12Bit 131201201201201201201201201201201201201201Counter = compare register (=2)22.11.4Timer 2 Output Mode 4

Biphase Modulator: Timer 2 Modulates the SSI Internal Data Output (SO) to Biphase CodeFigure 22-19.Biphase Modulation

TOG2SC8-bit SR-DataSOT2O0Bit 70Data: 0011010100111100110011Bit 052

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22.11.5

Timer 2 Output Mode 5

Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to Manchestercode

Figure 22-20.Manchester Modulation TOG2SC8-bit SR-DataSOT2O00Bit 700111100110011Bit 0Bit 0Bit 7Data: 0011010122.11.6

Timer 2 Output Mode 7

In this mode the timer overflow defines the period and the compare register defines the dutycycle. During one period only the first compare match occurrence is used to toggle the timer out-put flip-flop, until the overflow all further compare match are ignored. This avoids the situationthat changing the compare register causes the occurrence of several compare match during oneperiod. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all otherTimer2 modes are 8-bit.

PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O)Figure 22-21.PWM Modulation

Input clockCounter 2/2T2R0050255010025501502550502550100Counter 2/2CM2OVF2INT4T2OT1Tload the nextcompare valueT2CO2=150loadloadT2TT3TT1TT2T22.12Timer 2 Registers

Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock andits output function. All registers are indirectly addressed using extended addressing asdescribed in section “Addressing Peripherals” on page 32. The alternate functions of the PortsBP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer2modes require an input at T2I/BP41 or an output at T2O/BP42.

4552G–4BMCU–09/06

22.12.1Timer 2 Control Register (T2C)

Address: \"7\"hex - Subaddress: \"0\"hex

Bit3T2CS1

Bit2T2CS0

Bit1T2TS

Bit0T2R

Reset value: 0000b

T2CS1T2CS0

Timer 2 Clock Select bit 1Timer 2 Clock Select bit 0

Table 22-7.

0011

Timer 2 Clock Select Bits

0101

System clock (SYSCL)

Output signal of Timer 1 (T1OUT)Internal shift clock of SSI (SCL)Output signal of Timer 3 (TOG3)

T2CS1T2CS0Input Clock (CL 2/1) of Counter Stage 2/1

T2TS

Timer 2 Toggle with Start

T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start

T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R

Timer 2 Run

T2R = 0, Timer 2 stop and resetT2R = 1, Timer 2 run

T2R

22.12.2Timer 2 Mode Register 1 (T2M1)

Address: \"7\"hex - Subaddress: \"1\"hex

Bit3

T2D1

Bit2

T2D0

Bit1T2MS1

Bit0T2MS0

Reset value: 1111b

T2D1T2D0

Timer 2 Duty cycle bit 1Timer 2 Duty cycle bit 0

Table 22-8.

T2D11100

Timer 2 Duty Cycle Bits

T2D01010

Function of Duty Cycle Generator (DCG)Bypassed (DCGO0)Duty cycle 1/1 (DCGO1)Duty cycle 1/2 (DCGO2)Duty cycle 1/3 (DCGO3)

Additional Divider Effect

/1/2/3/4

T2MS1T2MS0

Timer 2 Mode Select bit 1Timer 2 Mode Select bit 0

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Table 22-9.

Mode12 3

Timer 2 Mode Select Bits

T2MS010 1

Clock Output (POUT)4-bit counter overflow (OVF1)4-bit compare output (CM1)

4-bit compare output (CM1)

Timer 2 Modes

12-bit compare counter; the DCG has to be bypassed in this mode

8-bit compare counter with 4-bit

programmable prescaler and duty cycle generator

8-bit compare counter clocked by

SYSCL or the external clock input T2I, 4-bit prescaler run, the counter 2/1 starts after writing mode 3

8-bit compare counter clocked by

SYSCL or the external clock input T2I, 4-bit prescaler stop and resets

T2MS111 0

4004-bit compare output (CM1)

22.12.3

Duty Cycle Generator

The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the dutycycle generator output depends on the duty cycle and the Timer 2 prescaler setting. TheDCG-stage can also be used as additional programmable prescaler for Timer 2.

Figure 22-22.DCG Output Signals

DCGINDCGO0DCGO1DCGO2DCGO322.12.4Timer 2 Mode Register 2 (T2M2)

Address: \"7\"hex - Subaddress: \"2\"hex

Bit3T2TOP

Bit2T2OS2

Bit1T2OS1

Bit0T2OS0

Reset value: 1111b

T2TOP

Timer 2 Toggle Output Preset

This bit allows the programmer to preset the Timer 2 output T2O.T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)Note: If T2R = 1, no output preset is possibleTimer 2 Output Select bit 2Timer 2 Output Select bit 1Timer 2 Output Select bit 0

T2OS2T2OS1T2OS0

4552G–4BMCU–09/06

Table 22-10.Timer 2 Output Select Bits

Output Mode12345678

T2OS211110000

T2OS111001100

T2OS010101010

Clock Output

Toggle mode: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Duty cycle burst generator 1: the DCG output signal (DCG0) is given to the output and gated by the output flip-flop (M2)Duty cycle burst generator 2: the DCG output signal (DCGO) is given to the output and gated by the SSI internal data output (SO)

Biphase modulator: Timer 2 modulates the SSI internal data output (SO) to Biphase code

Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code

SSI output: T2O is used directly as SSI internal data output (SO)

PWMmode: an 8-/12-bit PWM modeNotallowed

If one of these output modes is used the T2O alternate function of Port 4 must also be activated.

22.12.5

Timer 2 Compare and Compare Mode Registers

Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bitstage of Timer 2. The timer compares the contents of the compare register current counter valueand if it matches it generates an output signal. Dependent on the timer mode, this signal is usedto generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the nextcounter stage.

In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit com-pare value. In all other modes, the two compare registers work independently as a 4- and 8-bitcompare register.

When assigned to the compare register a compare event will be suppressed.

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22.12.6

Timer 2 Compare Mode Register (T2CM)

Address: \"7\"hex - Subaddress: \"3\"hex

Bit3T2OTM

Bit2T2CTM

Bit1T2RM

Bit0T2IM

Reset value: 0000b

T2OTM

Timer 2 Overflow Toggle Mask bitT2OTM = 0, disable overflow toggle

T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output

flip-flop (TOG2). If the T2OTM bit is set, only a counter overflow cangenerate an interrupt except on the Timer 2 output mode 7.Timer 2 Compare Toggle Mask bitT2CTM = 0, disable compare toggle

T2CTM = 1, enable compare toggle, a match of the counter with the compare

register toggles output flip-flop (TOG2). In Timer 2 output mode 7 andwhen the T2CTM bit is set, only a match of the counter with thecompare register can generate an interrupt.Timer 2 Reset Mask bit

T2RM = 0, disable counter reset

T2RM = 1, enable counter reset, a match of the counter with the compare register

resets the counterTimer 2 Interrupt Mask bit

T2IM = 0, disable Timer 2 interruptT2IM = 1, enable Timer 2 interrupt

T2CTM

T2RM

T2IM

Table 22-11.Timer 2 Toggle Mask Bits

Timer 2 Output Mode1, 2, 3, 4, 5 and 6 1, 2, 3, 4, 5 and 6 7

T2OTM01 x

T2CTMxx1

Timer 2 Interrupt SourceCompare match (CM2)Overflow (OVF2)Compare match (CM2)

22.12.7Timer 2 COmpare Register 1 (T2CO1)

Address: \"7\"hex - Subaddress: \"4\"hex

Write cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: 1111b

In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.

22.12.8

Timer 2 COmpare Register 2 (T2CO2) Byte Write

Address: \"7\"hex - Subaddress: \"5\"hex

First write cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: 1111b

Second write cycleBit 7Bit 6Bit 5Bit 4Reset value: 1111b

4552G–4BMCU–09/06

23.Timer 3

23.1

Features

•••••••••••

Figure 23-1.Timer 3

TOG2T3IT3EIMTwo Compare RegistersCapture Register

Edge Sensitive Input with Zero Cross Detection CapabilityTrigger and Single Action ModesOutput Control Modes

Automatically Modulation and Demodulation ModesFSK Modulation

Pulse Width Modulation (PWM)

Manchester Demodulation Together with SSIBiphase Demodulation Together with SSIPulse-width Demodulation Together with SSI

ControlINT5Capture registerNQCL3DT3SM1T3RM1T3IM1T3TM1: T3M18-bit counterRESCM318-bit comparatorControlC31C32CM32TOG3Compare register 1NQDT3SM2T3RM2T3IM2T3TM2: T3M2Compare register 2Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. Thetimer can be used as event counter, timer and signal generator. Its output can be programmedas modulator and demodulator for the serial interface. The two compare registers enable variousmodes of signal generation, modulation and demo-dulation. The counter can be driven by inter-nal and external clock sources. For external clock sources, it has a programmableedge-sensitive input which can be used as counter input, capture signal input or trigger input.This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPUcore -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable viaits capture register while it is running. In capture mode, the counter value can be captured by aprogrammable capture event from the Timer 3 input or Timer 2 output.

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A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counterstarts counting triggered by the external signal at its input. In single-action mode, the countercounts only one time up to the programmed compare match event. These modes are very usefulfor modulation, demodulation, signal generation, signal measurement and phase controlling. Forphase controlling, the timer input is protected against negative voltages and has zero-crossdetection capability.

Timer 3 has a modulator output stage and input functions for demodulation. As modulator itworks together with Timer 2 or the serial interface. When the shift register is used for modulationthe data shifted out of the register is encoded bitwise. In all demodulation modes, the decodeddata bits are shifted automatically into the shift register.

23.2Timer/Counter Modes

Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via the Timer3 Mode Register T3M.

In all these modes, the compare register and the compare-mode register belonging to it definethe counter value for a compare match and the action of a compare match. A match of the cur-rent counter value with the content of one compare register triggers a counter reset, a Timer 3interrupt or the toggling of the output flip-flop. The compare mode registers T3M1 and T3M2contain the mask bits for enabling or disabling these actions.

The counter can also be enabled to execute single actions with one or both compare registers. Ifthis mode is set the corresponding compare match event is generated only once after thecounter start.

Most of the timer modes use their compare registers alternately. After the start has been acti-vated, the first comparison is carried out via the compare register 1, the second is carried out viathe compare register 2, the third is carried out again via the compare register 1 and so on. Thismakes it easy to generate signals with constant periods and variable duty cycle or to generatesignals with variable pulse and space widths.

If single-action mode is set for one compare register, the comparison is always carried out afterthe first cycle via the other compare register.

The counter can be started and stopped via the control register T3C. This register also controlsthe initial level of the output before start. T3C contains the interrupt mask for a T3I inputinterrupt.

Via the Timer 3 clock-select register, the internal or external clock source can be selected. Thisregister selects also the active edge of the external input. An edge at the external input T3I cangenerate also an interrupt if the T3EIM bit is set and the Timer3 is stopped (T3R = 0) in the T3Cregister.

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Figure 23-2.Counter 3 Stage

TOG2T3IT3EIMControlINT5Capture registerNQCL3DT3SM1T3RM1T3IM1T3TM1: T3M18-bit counterRESCM318-bit comparatorControlC31C32CM32TOG3Compare register 1NQDT3SM2T3RM2T3IM2T3TM2: T3M2Compare register 2The status of the timer as well as the occurrence of a compare match or an edge detect of theinput signal is indicated by the status register T2ST. This allows identification of the interruptsource because all these events share only one timer interrupt.Timer 3 compares data values.

The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value can bem for each of the Timer 3 compare registers.The compare data value for the compare registers is:

m = x +1

0 ≤ x ≤ 255

23.2.1

Timer 3 – Mode 1: Timer/Counter

The selected clock from an internal or external source increments the 8-bit counter. In this mode,the timer can be used as event counter for external clocks at T3I or as timer for generating inter-rupts and pulses at T3O. The counter value can be read by the software via the capture register.

Figure 23-3.Counter Reset with Each Compare Match

T3RCounter 3CM31CM32INT5T3O0001230123450123012360

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Figure 23-4.Counter Reset with Compare Register 2 and Toggle with Start

CL3T3RCounter 3CM31CM32INT5T3OT3OToggleby start0001234567890123456Figure 23-5.Single Action of Compare Register 1

T3RCounter 3CM31CM32T3OToggle by start00123456789100120120120120120120120120120123.2.2

Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)

The counter is driven by an internal clock source. After starting with T3R, the first edge from theexternal input T3I starts the counter. The following edges at T3I load the current counter valueinto the capture register, reset the counter and restart it. The edge can be selected by the pro-grammable edge decoder of the timer input stage. If single-action mode is activated for one orboth compare registers the trigger signal restarts the single action.

Figure 23-6.Externally Triggered Counter Reset and Start Combined with Single-action Mode

T3RCounter 3T3EXCM31CM32T3O0000000012345678910012XXX012345678910012XXXX61

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23.2.3

Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)

The counter is driven by an internal or external (T3I) clock source. The output toggle signal ofTimer2 resets the counter. The counter value before the reset is saved in the capture register. Ifsingle-action mode is activated for one or both compare registers, the trigger signal restarts thesingle actions. This mode can be used for frequency measurements or as event counter withtime gate (see section “Combination Mode 10: Frequency Measurement or Event Counter withTime Gate” on page 91).

Figure 23-7.Event Counter with Time Gate

T3RT3ICounter 3TOG2T3CP-RegisterCapture value = 0Capture value = 11Capturevalue = 40012345678910110123401223.2.4

Timer 3 – Mode 4: Timer/Counter

The timer runs as timer/counter in mode 1, but its output T3O is used as output for the Timer 2output signal.

23.2.5

Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)

The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the Timer2 output signal.

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23.3

23.3.1

Timer 3 Modulator/Demodulator Modes

Timer 3 – Mode 6:

Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip-Flop (M2)

The Timer 3 counter is driven by an internal or external clock source. Its compare- and comparemode registers must be programmed to generate the carrier frequency via the output toggleflip-flop. The output toggle flip-flop of Timer2 is used to enable or disable the Timer 3 output.Timer 2 can be driven by the toggle output signal of Timer 3 or anyother clock source (see sec-tion “Combination Mode 11: Burst Modulation 1” on page 92).Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)

The Timer 3 counter is driven by an internal or external clock source. Its compare- and comparemode registers must be programmed to generate the carrier frequency via the output toggleflip-flop. The output (SO) of the SSI is used to enable or disable the Timer 3 output. The SSIshould be supplied with the toggle signal of Timer 2 (see section “Combination Mode 12: BurstModulation 2” on page 94).Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)

The two compare registers are used for generating two different time intervals. The SSI internaldata output (SO) selects which compare register is used for the output frequency generation. A\"0\" level at the SSI data output enables the compare register 1. A \"1\" level enables compare reg-ister 2. The compare- and compare-mode registers must be programmed to generate the twofrequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal ofTimer2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2counter is driven by the Counter3 (TOG3) (see section “Combination Mode 13: FSK Modula-tion” on page 94).

Figure 23-8.FSK Modulation

T3RCounter 3CM31CM32SOT3O010012340123401234012012012012012012012012340123.3.2

23.3.3

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23.3.4

Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register

The two compare registers are used for generating two different time intervals. The SSI internaldata output (SO) selects which compare register is used for the output pulse generation. In thismode both compare- and compare-mode registers must be programmed for generating the twopulse widths. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be suppliedwith a toggle signal of Timer 2. The counter is driven by an internal or external clock source (seesection “Combination Mode 7: Pulse-width Modulation (PWM)” on page 88).

Figure 23-9.Pulse-width Modulation

TOG2SIR0101SOSCOT3RCounter 3CM31CM32T3O000000000000000000012345678910111213141501234567891011121314150123423.3.5

Timer 3 – Mode 10: Manchester Demodulation/ Pulse-width Demodulation

For Manchester demodulation, the edge detection stage must be programmed to detect eachedge at the input. These edges are evaluated by the demodulator stage. The timer stage is usedto generate the shift clock for the SSI. The compare register 1 match event defines the correctmoment for shifting the state from the input T3I as the decoded bit into shift register – after thatthe demodulator waits for the next edge to synchronize the timer by a reset for the next bit. Thecompare register 2 can also be used to detect a time-out error and handle it with an interruptroutine (see section “Combination Mode 8: Manchester Demodulation/ Pulse-width Demodula-tion” on page 89).

Figure 23-10.Manchester Demodulation

Timer 3modeT3IT3EXSICM31=SCISR-DATA1BIT 01BIT 11BIT 20BIT 30BIT 41BIT 51BIT 60Synchronize1011Manchester demodulation mode10011064

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23.3.6

Timer 3 – Mode 11: Biphase Demodulation

In the Biphase demodulation mode, the timer operates like in Manchester demodulation mode.The difference is that the bits are decoded via a toggle flip-flop. This flip-flop samples the edge inthe middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop out-put into shift register (see section “Combination Mode 9: Biphase Demodulation” on page 90).

Figure 23-11.Biphase Demodulation

Timer 3modeT3IT3EXQ1=SICM31=SCIResetCounter 3SR-DATA0BIT 01BIT 11BIT 20BIT 31BIT 40BIT 51BIT 60Synchronize0011Biphase demodulation mode0101023.3.7

Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)

The counter is driven by an internal clock source and an edge at the external input T3I loads thecounter value into the capture register. The edge can be selected with the programmable edgedetector of the timer input stage. This mode can be used for signal and pulse measurements.

Figure 23-12.External Capture Mode

T3RT3ICounter 3T3CP-Register001234567891011121314151617181920212223242526272829303132333435363738394041Capture value = XCapture value = 17Capturevalue = 3565

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23.4Timer 3 Modulator for Carrier Frequency Burst Modulation

If the output stage operates as pulse-width modulator for the shift register, the output can bestopped with stage1 of Timer 2. For this task, the timer mode 3 must be used and the prescalermust be supplied by the internal shift clock of the shift register.

The modulator can be started with the start of the shift register (SIR = 0) and stopped either by ashift register stop (SIR = 1) or compare match event of stage 1 of Timer 2. For this task, theTimer 2 must be used in mode 3 and the prescaler stage must be supplied by the internal shiftclock of the shift register.Figure 23-13.Modulator 3

0TOG3T3SetResM312MUXT3OT3TOPSOM2SSI/ControlTimer 3 ModeT3O3OMSKT3M6 MUX 17 MUX 29 MUX 3other MUX 023.5Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals

The demodulator stage of Timer 3 can be used to decode Biphase, Manchester andpulse-width-coded signals.

Figure 23-14.Timer 3 Demodulator 3

T3MT3IDemodulator 3T3EXResSCISICM31Counter 3ResetCounter 3Control66

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23.6

23.6.1

Timer 3 Registers

Timer 3 Mode Register (T3M)

Address: \"B\"hex - Subaddress: \"0\"hex

Bit3T3M3

Bit2T3M2

Bit1T3M1

Bit0

T3M0

Reset value: 1111b

T3M3T3M2T3M1T3M0

Timer 3 Mode select bit 3Timer 3 Mode select bit 2Timer 3 Mode select bit 1Timer 3 Mode select bit 0

Table 23-1.

Mode12345678 910111213141516Note:1111111

Timer 3 Mode Select Bits

T3M21111000

T3M11100110

T3M010101010 1010101

T3M3Timer 3 Modes

Timer/counterwithareadaccess Timer/counter, external capture and external trigger restart mode (T3I)

Timer/counter, internal capture and internal trigger restart mode (TOG2)

Timer/countermode1withoutoutput(T2O->T3O)Timer/countermode2withoutoutput(T2O->T3O)BurstmodulationwithTimer2(M2)Burstmodulationwithshiftregister(SO)FSKmodulationwithshiftregister(SO)

Pulse-width modulation with shift register (SO) and Timer 2 (TOG2), internal trigger restart (SCO) -> counter resetManchester demodulation/pulse-width demodulation(1) (T2O -> T3O)

Biphasedemodulation(T2O->T3O)

Timer/counterwithexternalcapturemode(T3I)NotallowedNotallowedNotallowed

1 0000000

0 01111000

1100110

0000Notallowed

1.In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI modes are not allowed.

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23.6.2Timer 3 Control Register 1 (T3C) Write

Primary register address: \"C\"hex - Write

Bit3

Write

T3EIM

Bit2T3TOP

Bit1T3TS

Bit0T3R

Reset value: 0000b

T3EIM

Timer 3 Edge Interrupt Mask

T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to \"0\"

...................T3TOP = 1, sets toggle output (M3) to \"1\"...................Note: If T3R = 1, no output preset is possibleTimer 3 Toggle with Start .T3TS = 0, Timer 3 output is not toggled during the start

............T3TS = 1, Timer 3 output is toggled if started with T3RTimer 3 Run

............T3R = 0, Timer 3 stop and reset............T3R = 1, Timer 3 run

T3TOP

T3TST3R

23.6.3Timer 3 Status Register 1 (T3ST) Read

Primary register address: \"C\"hex - Read

Bit3

Read

- - -Bit2T3ED

Bit1T3C2

Bit0T3C1

Reset value: x000b

T3EDT3C2 T3C1Note:

Timer 3 Edge Detect

This bit will be set by the edge-detect logic of Timer 3 input (T3I)Timer 3 Compare 2

This bit will be set when a match occurs between Counter 3 and T3CO2Timer 3 Compare 1

This bit will be set when a match occurs between Counter 3 and T3CO1The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.

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23.6.4

Timer 3 Clock Select Register (T3CS)

Address: \"B\"hex - Subaddress: \"1\"hex

T3CS

Bit 3 T3E1

Bit 2T3E0

Bit 1T3CS1

Bit 0T3CS0

Reset value: 1111b

T3E1T3E0

Timer 3 Edge select bit 1Timer 3 Edge select bit 0

Table 23-2.

T3E11100

Timer 3 Edge Select Bits

T3E01010

Timer 3 Input Edge Select (T3I)–

Positive edge at T3I pinNegative edge at T3I pinEach edge at T3I pin

T3CS1Timer 3 Clock Source select bit 1T3CS0Timer 3 Clock Source select bit 0

Table 23-3.

T3CS11100

Timer 3 Clock Select Bits

TCS01010

Counter 3 Input Signal (CL3)System clock (SYSCL)

Output signal of Timer 2 (POUT)Output signal of Timer 1 (T1OUT)External input signal from T3I edge detect

23.6.5

Timer 3 Compare- and Compare-mode Register

Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3.The timer compares the content of the compare register with the current counter value. If bothmatch, it generates a signal. This signal can be used for the counter reset, to generate a timerinterrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. Foreach compare register, a compare-mode register exists. These registers contain mask bits toenable or disable the generation of an interrupt, a counter reset, or an output toggling with theoccurrence of a compare match of the corresponding compare register. The mask bits for acti-vating the single-action mode can also be located in the compare mode registers. Whenassigned to the compare register a compare event will be suppressed.

4552G–4BMCU–09/06

23.6.6Timer 3 Compare-Mode Register 1 (T3CM1)

Address: \"B\"hex - Subaddress: \"2\"hex

Bit3

T3CM1

T3SM1

Bit2T3TM1

Bit1T3RM1

Bit0T3IM1

Reset value: 0000b

T3SM1

Timer 3 Single action Mask bit 1

T3SM1 = 0, disables single-action compare mode

T3SM1 = 1, enables single-compare mode. After this bit is set, the compare

register (T3CO1) is used until the next compare match.Timer 3 compare Toggle action Mask bit 1T3TM1 = 0, disables compare toggle

T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare

Timer 3 Reset Mask bit 1

T3RM1 = 0, disables counter reset

T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare

T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.

T3TM1 T3RM1

T3IM1

T3CM1 contains the mask bits for the match event of the Counter3 compare register1.

23.6.7

Timer 3 Compare Mode Register 2 (T3CM2)

Address: \"B\"hex - Subaddress: \"3\"hex

Bit3

T3CM2

T3SM2

Bit2T3TM2

Bit1T3RM2

Bit0T3IM2

Reset value: 0000b

T3SM2

Timer 3 Single action Mask bit 2

T3SM2 = 0, disables single-action compare mode

T3SM2 = 1, enables single-compare mode. After this bit is set, the compare

register (T3CO2) is used until the next compare match.Timer 3 compare Toggle action Mask bit 2T3TM2 = 0, disables compare toggle

T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare

T3RM2 = 0, disables counter reset

T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare

T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.

T3TM2

T3RM2

T3IM2

T3CM2 contains the mask bits for the match event of Counter 3 compare register 2.

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The compare registers and corresponding counter reset masks can be used to program thecounter time intervals and the toggle masks can be used to program output signal. The sin-gle-action mask can also be used in this mode. It starts operating after the timer started withT3R.

23.6.8

Timer 3 COmpare Register 1 (T3CO1) Byte Write

Address: \"B\"hex - Subaddress: \"4\"hex

High Nibble

Second write cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: 1111b

Low Nibble

First write cycle

Bit 3

Bit 2

Bit 15

Bit 0

Reset value: 1111b

23.6.9Timer 3 COmpare Register 2 (T3CO2) Byte Write

Address: \"B\"hex - Subaddress: \"5\"hex

High Nibble

Second write cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: 1111b

Low Nibble

First write cycle

Bit 3

Bit 2

Bit 15

Bit 0

Reset value: 1111b

23.7Timer 3 Capture Register

The counter content can be read via the capture register. There are two ways to use the captureregister. In mode 1 and mode 4, it is possible to read the current counter value directly out of thecapture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer3 input or a signal from Timer 2 stores the current counter value into the capture register. Thiscounter value can be read from the capture register.

23.7.1Timer 3 CaPture Register (T3CP) Byte Read

Address: \"B\"hex - Subaddress: \"4\"hex

High Nibble

First read cycle

Bit 7

Bit 6

Bit 5

Bit 4

Reset value: xxxxb

Low Nibble

Second read cycle

Bit 3

Bit 2

Bit 15

Bit 0

Reset value: xxxxb

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23.8

23.8.1

Synchronous Serial Interface (SSI)

SSI Features

–2- and 3-wire NRZ

–2-wire multi-chip link mode (MCL), additional internal 2-wire link for multi-chip packaging solutions•WithTimer2

–Biphase modulation–Manchester modulation–Pulse-width demodulation–Burst modulation•WithTimer3

–Pulse-width modulation (PWM)–FSK modulation–Biphase demodulation–Manchester demodulation–Pulse-width demodulation–Pulse position demodulation

23.8.2

SSI Peripheral Configuration

The synchronous serial interface (SSI) can be used either for serial communication with external

devices such as EEPROMs, shift registers, display drivers, other microcon-trollers, or as ameans for generating and capturing on-chip serial streams of data. External data communicationtakes place via the Port 4 (BP4),a multi-functional port which can be software configured by writ-ing the appropriate control word into the P4CR register. The SSI can be configured in any of the following ways:

1.2-wire external interface for bi-directional data communication with one data terminal

and one shift clock. The SSI uses the Port BP43 as a bi-directional serial data line (SD) and BP40 as shift clock line (SC).2.3-wire external interface for simultaneous input and output of serial data, with a serial

input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input.). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in mode 6).3.Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is capable

of performing a variety of data modulation and demodulation functions (see section Timer). The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. Serial demodu-lated data can be serially captured in the SSI and read by the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI can only be used as demodulator.

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4.Internal Multi-Chip Link pads (MCL) – the SSI can also be used as an interchip data

interface for use in single package multi-chip modules or hybrids. For such applications, the SSI is provided with two dedicated pads (MCL_SD and MCL_SC) which act as a two-wire chip-to-chip link. The internal MCL can be activated by the MCL control bit. Should these MCL pads be used by the SSI, the standard SD and SC pins are not required and the corresponding Port4 ports are available as conventional data ports.Figure 23-15.Block Diagram of the Synchronous Serial Interface

I/O-busTimer 2 / Timer 3SIC1SIC2SISCSOControlSCSSI-ControlOutput8-bit Shift RegisterSILSBMCL_SDSDINT3SCMCL_SCTOG2POUTT1OUTSYSCL/2SOShift_CLSISCIMSBSTBTransmitBufferI/O-busSRBReceiveBuffer23.8.3

General SSI Operation

The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers – thereceive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for inter-mediate storage of data to be serially output. Both buffers are directly accessable by software.Transferring the parallel buffer data into and out of the shift register is controlled automatically bythe SSI control, so that both single byte transfers or continuous bit streams can be supported.

The SSI can generate the shift clock (SC) either from one of several on-chip clock sources oraccept an external clock. The external shift clock is output on, or applied to the Port BP40.Selection of an external clock source is performed by the Serial Clock Direction control bit(SCD). In the combinational modes, the required clock is selected by the corresponding timermode.

The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a 9-bitMulti-Chip Link Mode (MCL), containing 8-bit data and 1-bit acknowledge, and a corresponding8-bit MCL mode without acknowledge. In both MCL modes the data transmission begins after avalid start condition and ends with a valid stop condition.

External SSI clocking is not supported in these modes. The SSI should thus generate and hasfull control over the shift clock so that it can always be regarded as an MCL Bus Master device.All directional control of the external data port used by the SSI is handled automatically and isdependent on the transmission direction set by the Serial Data Direction (SDD) control bit. Thiscontrol bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX)mode.

Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. Inthe 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram forhandshaking purposes (see section “MCL Bus Protocol” on page 77).

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At the beginning of every telegram, the SSI control loads the transmit buffer into the shift registerand proceeds immediately to shift data serially out. At the same time, incoming data is shiftedinto the shift register input. This incoming data is automatically loaded into the receive bufferwhen the complete telegram has been received. Thus, data can be simultaneously received andtransmitted if required.

Before data can be transferred, the SSI must first be activated. This is performed by means ofthe SSI reset control (SIR) bit. All further operation then depends on the data directional mode(TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface ReadyStatus Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer(in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting istemporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0).The SRDY status will then automatically be set back to ‘1’ and data shifting resumed as soon asthe application software loads the new data into the transmit register (in TX mode) or frees theshift register by reading it into the receive buffer (in RX mode).

A further activity status (ACT) bit indicates the present status of the serial communication. TheACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions arecurrently being generated. Both the current SRDY and ACT status can be read in the SSI statusregister. To deactivate the SSI, the SIR bit must be set high.

23.8.4

8-bit Synchronous Mode

Figure 23-16.8-bit Synchronous Mode

SC(Rising edge)SC(Falling edge)DATA0Bit 7SD/TO20Bit 7Data: 001101010110100110101Bit 01Bit 0In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see sec-tion “SSI Peripheral Configuration” on page 72). The serial data (SD) is received or transmittedin NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choiceof clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that thetransmission edge refers to the SC clock edge with which the SD changes. To avoid clock skewproblems, the incoming serial input data is shifted in with the opposite edge.

When used together with one of the timer modulator or demodulator stages, the SSI must be setin the 8-bit synchronous mode 1.

In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and theincoming serial data is shifted into the shift register. This first telegram is automatically trans-ferred into the receive buffer and the SRDY set to 0 indicating that the receive buffer containsvalid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shift-ing in the following 8-bit telegram. If, during this time the first telegram has been read by thecontroller, the second telegram will also be transferred in the same way into the receive buffer

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and the SSI will continue clocking in the next telegram. Should, however, the first telegram nothave been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram inthe shift register until a certain point of time when the controller is able to service the receivebuffer. In this way no data is lost or overwritten.

Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch thepresent contents of the shift register into the receive buffer. This can be used for clocking in adata telegram of less than 8 bits in length. Care should be taken to read out the final complete8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and termi-nating the reception. After termination, the shift register contents will overwrite the receivebuffer.

Figure 23-17.Example of 8-bit Synchronous Transmit Operation

SCmsbSDlsb0msblsbmsblsb07654321765432107654321tx data 1SIRtx data 2tx data 3SRDYACTInterrupt(IFN = 0)Interrupt(IFN = 1)Write STB(tx data 1)Write STB(tx data 2)Write STB(tx data 3)Figure 23-18.Example of 8-bit Synchronous Receive Operation

SCmsbSDlsbmsblsbmsblsb7654321076543210rx data 1rx data 2765432107654rx data 3SIRSRDYACTInterrupt(IFN = 0)Interrupt(IFN = 1)Read SRB(rx data 1)Read SRB(rx data 2)Read SRB(rx data 3)75

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23.8.5

9-bit Shift Mode (MCL)

In the 9-bit shift mode, the SSI is able to handle the MCL protocol described below. It alwaysoperates as an MCL master device, i.e., SC is always generated and output by the SSI. Both theMCL start and stop conditions are automatically generated whenever the SSI is activated ordeactivated by the SIR bit. In accordance with the MCL protocol, the output data is alwayschanged in the clock low phase and shifted in on the high phase.

Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direc-tion for the first word must be set using the SDD control bit. The state of this bit controls thedirection of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending onthe selected direction, either clocked into or out of the shift register. During the 9th clock period,the port direction is automatically switched over so that the corresponding acknowledge bit canbe shifted out or read in. In transmit mode, the acknowledge bit received from the device is cap-tured in the SSI Status Register (TACK) where it can be read by the controller. In receive mode,the state of the acknowledge bit to be returned to the device is predetermined by the SSI StatusRegister (RACK).

Changing the directional mode (TX/RX) should not be performed during the transfer of an MCLtelegram. One should wait until the end of the telegram which can be detected using the SSIinterrupt (IFN = 1) or by interrogating the ACT status.

Once started, a 9-bit telegram will always run to completion and will not be prematurely termi-nated by the SIR bit. So, if the SIR bit is set to \"1\" in telegram, the SSI will complete the currenttransfer and terminate the dialog with an MCL stop condition.Figure 23-19.Example of MCL Transmit Dialog

StartSCmsbSDlsbmsblsbStop76543210Atx data 176543210Atx data 2SRDYACTInterrupt(IFN = 0)Interrupt(IFN = 1)SIRSDDWrite STB(tx data 1)Write STB(tx data 2)76

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Figure 23-20.Example of MCL Receive Dialog

StartSCmsbSDlsbmsblsbStop76543210Atx data 176543210Arx data 2SRDYACTInterrupt(IFN = 0)Interrupt(IFN = 1)SIRSDDWrite STB(tx data 1)Read SRB(rx data 2)23.8.6

8-bit Pseudo MCL Mode

In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl-edge bit which is never expected or transmitted.MCL Bus Protocol

The MCL protocol constitutes a simple 2-wire bi-directional communication highway via whichdevices can communicate control and data information. Although the MCL protocol can supportmulti-master bus configurations, the SSI in MCL mode is intended for use purely as a mastercontroller on a single master bus system. So all reference to multiple bus control and bus con-tention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge bit. Nor-mally the communication channel is opened with a so-called start condition, which initializes alldevices connected to the bus. This is then followed by a data telegram, transmitted by the mas-ter controller device. This telegram usually contains an 8-bit address code to activate a singleslave device connected onto the MCL bus. Each slave receives this address and compares itwith its own unique address. The addressed slave device, if ready to receive data, will respondby pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowl-edge. The controller detecting this affirmative acknowledge then opens a connection to therequired slave. Data can then be passed back and forth by the master controller, each 8-bit tele-gram being acknowledged by the respective recipient. The communication is finally closed bythe master device and the slave device put back into standby by applying a stop condition ontothe bus.

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Figure 23-21.MCL Bus Protocol 1

(1)SC(2)(4)(4)(3)(1)SDStartconditionDatavalidDatachangeDatavalidStopconditionBus not busy (1)Start data transfer (2)Stop data transfer (3)Data valid (4)

Both data and clock lines remain HIGH.

A HIGH to LOW transition of the SD line while the clock (SC) is HIGH defines a START condition.

A LOW to HIGH transition of the SD line while the clock (SC)is HIGH defines a STOP condition.

The state of the data line represents valid data when, after START condition, the data line is stable for the duration of the HIGH period of the clock signal.

All address and data words are serially transmitted to and from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to acknowledge word receipt.

Acknowledge

Figure 23-22.MCL Bus Protocol 2

SC1n89SDStart1st Bit8th BitACKStop23.8.8SSI Interrupt

The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,transmitbuffer empty or receive buffer full), the end of SSI data telegram or on the falling edge of theSC/SD pins on Port 4 (see section “Port 4 Control Register (P4CR) Byte Write” on page 40). SSIinterrupt selection is performed by the Interrupt FunctioN control bit (IFN). The SSI interrupt isusually used to synchronize the software control of the SSI and inform the controller of thepresent SSI status. The Port 4 interrupts can be used together with the SSI or, if the SSI itself isnot required, as additional external interrupt sources. In either case this interrupt is capable ofwaking the controller out of sleep mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Inter-rupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits inP4CR register.

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23.8.9

Modulation and Demodulation

If the shift register is used together with Timer 2 or Timer3 for modulation or demodulation pur-poses, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can beused as conventional bi-directional ports.

The modulation and demodulation stages, if enabled, operate as soon as the SSI is activated(SIR = 0) and cease when deactivated (SIR = 1).

Due to the byte-orientated data control, the SSI (when running normally) generates serial bitstreams which are submultiples of 8 bits. An SSI output masking (OMSK) function permits; how-ever, the generation of bit streams of any length. The OMSK signal is derived indirectly from the4-bit prescaler of the Timer 2 and masks out a programmable number of unrequired trailing databits during the shifting out of the final data word in the bit stream. The number of non-maskeddata bits is defined by the value pre-programmed in the prescaler compare register. To use out-put masking, the modulator stop mode bit (MSM) must be set to \"0\" before programming thefinal data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescalerwhen this final word is shifted out. On reaching the compare value, the prescaler triggers theOMSK signal and all following data bits are blanked.

23.8.10

Internal 2-wire Multi-chip Link

Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be used aschip-to-chip link for multi-chip applications. These pads can be activated by setting the MCL-bitin the SISC-register.

Figure 23-23.Multi-chip Link

U505MSCLSDAMulti chip linkMCL_SCVDDBP40/SCMCL_SDVSSBP43/SDMicrocontrollerBP10BP13Figure 23-24.SSI Output Masking Function

CL2/1SCLCompare 2/1CM1OMSKControlSCSSI-controlOutput8-bit shift registerSILSBSO4-bit counter 2/1Timer 2TOG2POUTT1OUTSYSCLSO/2Shift_CLMSB79

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23.9

23.9.1

Serial Interface Registers

Serial Interface Control Register 1 (SIC1)

Auxiliary register address: \"9\"hex

Bit3SIR

Bit2SCD

Bit1SCS1

Bit0SCS0

Reset value: 1111b

SIR

Serial Interface ResetSIR = 1, SSI inactiveSIR = 0, SSI active

Serial Clock Direction

SCD = 1, SC line used as outputSCD = 0, SC line used as input

SCD

Note: This bit has to be set to \"1\" during the MCL mode and the Timer 3 mode 10 or 11

SCS1SCS0

Serial Clock source Select bit 1Serial Clock source Select bit 0

Note: with SCD = \"0\" the bits SCS1 and SCS0 are insignificant

Table 23-4.

SCS111

Serial Clock Source Select Bits

SCS010

1 0

Internal Clock for SSISYSCL/2T1OUT/2POUT/2TOG2/2

0 0

•In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1).

•Setting SIR bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only).

•In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition.

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23.9.2

Serial Interface Control Register 2 (SIC2)

Auxiliary register address: \"A\"hex

Bit3MSM

Bit2SM1

Bit1SM0

Bit0SDD

Reset value: 1111b

MSM

Modular Stop Mode

MSM = 1, modulator stop mode disabled (output masking off)

MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub-multiples of 8bits.Serial Mode control bit 1Serial Mode control bit 0

SM1SM0

Table 23-5.

Mode1234

1100

Serial Mode Control Bits

SM01010

SSI Mode

8-bit NRZ-Data changes with the rising edge of SC8-bit NRZ-Data changes with the falling edge of SC9-bit two-wire MCL mode

8-bit two-wire MCL mode (no acknowledge)

SM1

SDD

Serial Data Direction

SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set

............by a transmit buffer write access.

SDD = 0, receive mode – .SD line used as input (receive data). SRDY is set

............by a receive buffer read access

Note: SDD controls port directional control and defines the reset function for the SRDY flag

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23.9.3Serial Interface Status and Control Register (SISC)

Primary register address: \"A\"hex

WriteRead

Bit 3MCL- - -Bit 2RACKTACK

Bit 1SIMACT

Bit 0IFNSRDY

Reset value: 1111bReset value: xxxxb

MCL

Multi-Chip Link activation

MCL = 1,multi-chip link disabled. This bit has to be set to \"0\" during

transactions to/from EEPROM

MCL = 0, connects SC and SD additionally to the internal multi-chip link padsReceive ACKnowledge status/control bit for MCL modeRACK = 0, transmit acknowledge in next receive telegramRACK = 1, transmit no acknowledge in last receive telegramTransmit ACKnowledge status/control bit for MCL modeTACK = 0, acknowledge received in last transmit telegramTACK = 1, no acknowledge received in last transmit telegramSerial Interrupt Mask

SIM = 1, disable interrupts

SIM = 0, enable serial interrupt. An interrupt is generated.

Interrupt FuNction

IFN = 1, the serial interrupt is generated at the end of telegram

IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer

becomes empty/full in transmit/receive mode)Serial interface buffer ReaDY status flag

SRDY = 1,in receive mode: receive buffer empty

in transmit mode: transmit buffer full

SRDY = 0, in receive mode: receive buffer full

in transmit mode: transmit buffer empty

Transmission ACTive status flag

ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions

are currently in progress.

ACT = 0, transmission is inactive

RACK

TACK

SIM

IFN

SRDY

ACT

23.9.4Serial Transmit Buffer (STB) – Byte Write

Primary register address: \"9\"hex

First write cycleSecond write cycle

Bit 3Bit 7

Bit 2Bit 6

Bit 1Bit 5

Bit 0Bit 4

Reset value: xxxxbReset value: xxxxb

The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register andstarts shifting with the most significant bit.

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23.9.5

Serial Receive Buffer (SRB) – Byte Read

Primary register address: \"9\"hex

First read cycleSecond read cycle

Bit 7Bit 3

Bit 6Bit 2

Bit 5Bit 1

Bit 4Bit 0

Reset value: xxxxbReset value: xxxxb

The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first)

and loads content into the receive buffer when complete telegram has been received.

24.Combination Modes

The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multi-tude of modes in which the timers and serial interface can work together.

The 8-bit wide serial interface operates as shift register for modulation and demodulation. Themodulator and demodulator units work together with the timers and shift the data bits into or outof the shift register.

24.1Combination Mode Timer 2 and SSI

Figure 24-1.Combination Timer 2 and SSI

I/O-busP4CRT2IT2M1T2M2DCGOSYSCLT1OUTTOG3SCLCL2/14-bit counter 2/1RESOVF1POUTCL2/2T2ODCG8-bit counter 2/2RESOVF2TOG2INT4OutputT2CCompare 2/1Timer 2 - controlPOUTCM1Compare 2/2MOUTBiphase-,Manchester-modulatorT2CO1TOG2T2CMT2CO2SOTimer 2modulatoroutput-stageControlI/O-busSIC1TOG2POUTT1OUTSYSCLSCLISIC2SISCControlINT3SOSCSSI-controlMCL_SCOutput8-bit shift registerSILSBSCLSOMSBMCL_SDSDShift_CLSTBTransmitbufferI/O-busSRBReceivebuffer83

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24.1.1

Combination Mode 1: Burst Modulation

SSI mode 1:

Timer 2 mode 1, 2, 3 or 4:Timer 2 output mode 3:

8-bit NRZ and internal data SO output to the Timer 2 modulator stage

8-bit compare counter with 4-bit programmable prescaler and DCG

Duty cycle burst generator

Figure 24-2.Carrier Frequency Burst Modulation with the SSI Internal Data Output

DCGOCounter 2TOG2SOT2OBit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8Bit 9Bit 10Bit 11Bit 12Bit 131201201201201201201201201201201201201201Counter = compare register (=2)24.1.2

Combination Mode 2: Biphase Modulation 1

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4:Timer 2 output mode 4:

8-bit compare counter with 4-bit programmable prescalerThe modulator 2 of Timer 2 modulates the SSI internal data output to Biphase code

Figure 24-3.Biphase Modulation 1

TOG2SC8-bit SR-dataSOT2O0Bit 70Data: 0011010100111100110011Bit 084

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24.1.3

Combination Mode 3: Manchester Modulation 1

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4:Timer 2 output mode 5:

8-bit compare counter with 4-bit programmable prescalerThe modulator 2 of Timer 2 modulates the SSI internal data output to Manchester code

Figure 24-4.Manchester Modulation 1

TOG2SC8-bit SR-dataSOT2O00Bit 700111100110011Bit 0Bit 0Bit 7Data: 0011010124.1.4

Combination Mode 4: Manchester Modulation 2

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 3:Timer 2 output mode 5:

8-bit compare counter and 4-bit prescaler

The modulator 2 of Timer 2 modulates the SSI data output to Manchester code

The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2.The SSI has a special mode to supply the prescaler with the shift clock. The control output signal(OMSK) of the SSI is used as stop signal for the modulator. Figure 24-5 shows an example for a12-bit Manchester telegram.

Figure 24-5.Manchester Modulation 2

SCLIBuffer fullSIRSOSCMSMTimer 2Mode 3SCLCounter2/1OMSKT2O00000Counter 2/1 = Compare Register 2/1 (= 4)000012Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 034012385

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24.1.5

Combination Mode 5: Biphase Modulation 2

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 3:Timer 2 output mode 4:

8-bit compare counter and 4-bit prescaler

The modulator 2 of Timer 2 modulates the SSI data output to Biphase code

The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2.The SSI has a special mode to supply the prescaler via the shift clock. The control output signal(OMSK) of the SSI is used as stop signal for the modulator. Figure 24-6 shows an example for a13-bit Biphase telegram.

Figure 24-6.Biphase Modulation

SCLIBuffer fullSIRSOSCMSMTimer 2Mode 3SCLCounter2/1OMSKT2O00000Counter 2/1 = Compare Register 2/1 (= 5)000012345012Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 086

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24.2

Combination Mode Timer 3 and SSI

Figure 24-7.Combination Timer 3 and SSI I/O-busT3CST3MT3IT3EXSCT3IDemodu-SIlator 3T3CPCP3CM31RESSYSCLT3EXCL3T1OUT8-bit counter 3T3CT3STINT5POUTRESTOG3SOT3OCompare 3/1Compare 3/2Timer 3 - controlControlModulator 3M2T3CO1T3CO2T3CM1T3CM2SISCSIC1SIC2SISCControlTOG2INT3POUTSCSCLIT1OUTSSI-controlSYSCLMCL_SCSOOutputMCL_SDSIShift_CLMSB8-bit shift registerSILSBSTBSRBTransmit bufferI/O-busReceive buffer4552G–4BMCU–09/06

24.2.1

Combination Mode 6: FSK Modulation

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 8:

FSK modulation with shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data outputselects which compare register is used for the output frequency generation. A \"0\" level at theSSI data output enables the compare register 1 and a \"1\" level enables the compare register 2.The compare and compare mode registers must be programmed to generate the two frequen-cies via the output toggle flip-lop. The SSI can be supplied with the toggle signal of Timer2 orany other clock source. The Timer 3 counter is driven by an internal or external clock source.Figure 24-8.FSK Modulation

T3RCounter 3CM31CM32SOT3O01234012340120120120120120120120120123401234001024.2.2

Combination Mode 7: Pulse-width Modulation (PWM)

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 9:

Pulse-width modulation with the shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data outputselects which compare register is used for the output pulse generation. In this mode, both com-pare and compare mode registers must be programmed to generate the two pulse width. It isalso useful to enable the single-action mode for extreme duty cycles. Timer 2 is used asbaudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with thetoggle signal of Timer2. The counter is driven by an internal or external clock source.Figure 24-9.Pulse-width Modulation

TOG2SIR0101SOSCOT3RCounter 3CM31CM32T3O000000000000000000012345678910111213141501234567891011121314150123488

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

24.2.3

Combination Mode 8: Manchester Demodulation/ Pulse-width Demodulation

SSI mode 1:8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 10:

Manchester demodulation/pulse-width demodulation with Timer 3

For Manchester demodulation, the edge detection stage must be programmed to detect eachedge at the input. These edges are evaluated by the demodulator stage. The timer stage is usedto generate the shift clock for the SSI. A compare register 1 match event defines the correctmoment for shifting the state from the input T3I as the decoded bit into shift register. After that,the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. Thecompare register 2 can be used to detect a time error and handle it with an interrupt routine.Before activating the demodulator mode the timer and the demodulator stage must be synchro-nized with the bitstream. The Manchester code timing consists of parts with the half bitlengthand the complete bitlength. A synchronization routine must start the demodulator after an inter-val with the complete bitlength.

The counter can be driven by any internal clock source. The output T3O can be used by Timer 2in this mode. The Manchester decoder can also be used for pulse-width demodulation. The inputmust programmed to detect the positive edge. The demodulator and timer must be synchronizedwith the leading edge of the pulse. After that a counter match with the compare register 1 shiftsthe state at the input T3I into the shift register. The next positive edge at the input restarts thetimer.

Figure 24-10.Manchester Demodulation

Timer 3modeT3IT3EXSICM31=SCISR-DATA1Bit 71Bit 61Bit 50Bit 40Bit 31Bit 21Bit 10Bit 0Synchronize1011Manchester demodulation mode10011089

4552G–4BMCU–09/06

24.2.4

Combination Mode 9: Biphase Demodulation

SSI mode 1:8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 11:

Biphase demodulation with Timer 3

In the Biphase demodulation mode the timer works like in the Manchester demodulation mode.The difference is that the bits are decoded with the toggle flip-flop. This flip-flop samples theedge in the middle of the bitframe and the compare register 1 match event shifts the toggleflip-flop output into shift register. Before activating the demodulation the timer and the demodula-tion stage must be synchronized with the bitstream. The Biphase code timing consists of partswith the half bitlength and the complete bitlength. The synchronization routine must start thedemodulator after an interval with the complete bitlength.

The counter can be driven by any internal clock source and the output T3O can be used byTimer 2 in this mode.

Figure 24-11.Biphase Demodulation

Timer 3modeT3IT3EXQ1=SICM31=SCIResetCounter 3SR-DATA0Bit 71Bit 61Bit 50Bit 41Bit 30Bit 21Bit 10Bit 0Synchronize0011Biphase demodulation mode0101090

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

24.3

Combination Mode Timer 2 and Timer 3

Figure 24-12.Combination Timer 2 and Timer 3

I/O-busT3CST3IT3MT3EXT3IT3CPT3EXSYSCLT1OUTPOUTCL3SCIDemodu-lator 3SICP3CM31REST3CT3STINT5TOG3SO8-bit counter 3RESCompare 3/1Compare 3/2Timer 3 - controlTOG2T3CO1T3CO2T3CM1T3CM2I/O-busT3OModulator 3ControlM2SSIT2ITOG3SYSCLT1OUTSCLT2CP4CRT2M1DCGOT2M2T2OCL2/14-bit counter 2/1RESOVF1CL2/2POUTDCG8-bit counter 2/2RESOVF2TOG2OUTPUTMOUTM2Biphase-,Manchester-modulatorSOCompare 2/1CM1Timer 2 - controlPOUTCompare 2/2INT4T2CO1I/O-busSSIT2CMT2CO2Timer 2modulator 2output-stageSSIControl(RE, FE, SCO, OMSK)24.3.1

Combination Mode 10: Frequency Measurement or Event Counter with Time Gate

Timer 2 mode 1/2:12-bit compare counter/8-bit compare counter and 4-bit prescaler

Timer 2 output mode 1/6:Timer 3 mode 3:

Timer 2 compare match toggles (TOG2) to the Timer 3Timer/Counter; internal trigger restart and internal

capture (with Timer 2 TOG2-signal)

The counter is driven by an external (T3I) clock source. The output signal (TOG2) of Timer 2resets the counter. The counter value before reset is saved in the capture register. If sin-gle-action mode is activated for one or both compare registers, the trigger signal restarts alsothe single actions. This mode can be used for frequency measurements or as event counter withtime gate.

4552G–4BMCU–09/06

Figure 24-13.Frequency Measurement

T3RT3ICounter 30012345678910111213141516170123456789101112131415161718012345TOG2T3CP-RegisterCapture value = 0Capture value = 17Capt. value = 18Figure 24-14.Event Counter with Time Gate

T3RT3ICounter 3TOG2T3CP-RegisterCapture value = 0Capture value = 11Cap. val. = 40012345678910110123401224.3.2

Combination Mode 11: Burst Modulation 1

Timer 2 mode 1/2:12-bit compare counter/8-bit compare counter and 4-bit prescaler

Timer 2 output mode 1/6:Timer 3 mode 6:

Timer 2 compare match toggles the output flip-flop (M2)

to the Timer 3

Carrier frequency burst modulation controlled by Timer 2 output (M2)

The Timer 3 counter is driven by an internal or external clock source. Its compare and comparemode registers must be programmed to generate the carrier frequency with the output toggleflip-flop. The output toggle flip-flop (M2) of Timer 2 is used to enable and disable the Timer 3 out-put. The Timer 2 can be driven by the toggle output signal of Timer3 (TOG3) or any other clocksource.

Figure 24-15.Burst Modulation 1

CL3Counter 3CM1CM2TOG3M3Counter 2/2TOG2M2T3O3012330123010123450101234501012345010150101501015010150101501015010150101501015010192

ATAR862-4

4552G–4BMCU–09/06

ATAR862-4

24.4

Combination Mode Timer 2, Timer 3 and SSI

Figure 24-16.Combination Timer 2, Timer3 and SSI

I/O-busT3CST3MT3IT3EXSCIT3IDemodu-SIlator 3T3CPCP3CM31REST3EXSYSCLCL38-bit Counter 3INT5T1OUTT3CT3STPOUTTOG3RESSOT3OCompare 3/1Compare 3/2Timer 3 - controlControlModulator 3TOG2M2T3CO1T3CO2T3CM1T3CM2I/O-busSSIT2IP4CRT2M1T2M2DCGOTOG3T2OSYSCLCL2/1CL2/2T1OUT4-bit Counter 2/1DCG8-bit Counter 2/2OUTPUTSCLRESOVF1POUTRESOVF2MOUTTOG2T2CCompare 2/1Timer 2 - controlCompare 2/2M2INT4Biphase-,CM1POUTManchester-modulatorT2CO1T2CMT2CO2SOControlI/O-busControlmodulator 2Timer 2output-stageSIC1SIC2SISC(RE, FE,SCO, OMSK)TOG2INT3SCPOUTSCLIT1OUTSSI-controlSYSCLMCL_SCSOOutputSCLSIMCL_SDSIShift_CLMSB8-bit shift registerLSBSTBSRBTransmit bufferI/O-busReceive buffer4552G–4BMCU–09/06

24.4.1

Combination Mode 12: Burst Modulation 2

SSI mode 1:8-bit shift register internal data output (SO) to the Timer 3

Timer 2 output mode 2:Timer 2 output mode 1/6:Timer 3 mode 7:

8-bit compare counter and 4-bit prescaler

Timer 2 compare match toggles (TOG2) to the SSI

Carrier frequency burst modulation controlled by the internal

output (SO) of SSI

The Timer 3 counter is driven by an internal or external clock source. Its compare and comparemode registers must be programmed to generate the carrier frequency with the output toggleflip-flop (M3). The internal data output (SO) of the SSI is used to enable and disable the Timer 3output. The SSI can be supplied with the toggle signal of Timer2.

Figure 24-17.Burst Modulation 2

CL3Counter 3CM31CM32TOG3M3Counter 2/2TOG2SOT3O3012330123010123450101234501012345010150101501015010150101501015010150101501015010124.4.2

Combination Mode 13: FSK Modulation

SSI mode 1:

Timer 2 output mode 3:Timer 2 output mode 1/6:Timer 3 mode 8:

8-bit shift register internal data output (SO) to the Timer 3 8-bit compare counter and 4-bit prescaler

Timer 2 4-bit compare match signal (POUT) to the SSIFSK modulation with shift register data output (SO)

The two compare registers are used to generate two different time intervals. The SSI data outputselects which compare register is used for the output frequency generation. A \"0\" level at theSSI data output enables the compare register 1 and a \"1\" level enables the compare register 2.The compare- and compare mode registers must be programmed to generate the two frequen-cies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer2 orany other clock source. The Timer 3 counter is driven by an internal or external clock source.

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ATAR862-4

Figure 24-18.FSK Modulation

T3RCounter 3CM31CM32SOT3O010012340123401234012012012012012012012012340124.5Microcontroller Block

The microcontroller block is a multichip device which offers a combination of a MARC4-basedmicrocontroller and a serial E2PROM data memory in a single package. A microcontroller isused and as serial E2PROM the U505M. Two internal lines can be used as chip-to-chip link in asingle package. The maximum internal data communication frequency between the microcon-troller block and the U505M over the chip link (MCL_SC and MCL_SD) is fSC_MCL = 500 kHz.The microcontroller and the EEPROM portions of this multi-chip device are equivalent to theirrespective individual component chips, except for the electrical specification.

24.5.1

Internal 2-wire Multi-chip Link

Figure 24-19.Link between the Microcontroller Block and U505M

U505MSCLSDAMulti chip linkMCL_SCVDDBP40/SCMCL_SDVSSBP43/SDMicrocontrollerBP10BP1395

4552G–4BMCU–09/06

24.6U505M EEPROM

The U505M is a 512-bit EEPROM internally organized as 32×16-bits. The programming volt-age as well as the write-cycle timing is generated on-chip. The U505M features a serial interfaceallowing operation on a simple two-wire bus with an MCL protocol. Its low power consumptionmakes it well suited for battery applications.Figure 24-20.Block Diagram EEPROM

ATAR862-4 Timing controlHV-generatorVDDAddressEEPROMVcontrol32 x 16SSModecontrol16-bit read/write bufferSCLI/O8-bit data registerSDAcontrol4552G–4BMCU–09/06

ATAR862-4

24.7

Serial Interface

The U505M has a two-wire serial interface (TWI) to the microcontroller for read and writeaccesses to the EEPROM. The U505M is considered to be a slave in all these applications. Thatmeans, the controller has to be the master that initiates the data transfer and provides the clockfor transmit and receive operations.

The serial interface is controlled by the microcontroller block which generates the serial clockand controls the access via the SCL line and SDA line. SCL is used to clock the data into andout of the device. SDA is a bi-directional line that is used to transfer data into and out of thedevice. The following protocol is used for the data transfers.

24.7.1

Serial Protocol

•Data states on the SDA line changing only while SCL is low.

•Changes on the SDA line while SCL is high are interpreted as START or STOP condition.•A START condition is defined as high to low transition on the SDA line while the SCL-line is high.

•A STOP condition is defined as low to high transition on the SDA line while the SCL line is high.

•Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to standby mode.

•A receiving device generates an acknowledge (A) after the reception of each byte. This requires an additional clock pulse, generated by the master. If the reception was successful the receiving master or slave device pulls down the SDA line during that clock cycle. If an acknowledge is not detected (N) by the interface in transmit mode, it will terminate further data transmissions and go into receive mode. A master device must finish its read operation by a non-acknowledge and then send a stop condition to bring the device into a known state.Figure 24-21.MCL Protocol

SCLSDAStandStartbyconditionDatavalidData/DatachangeacknowledgevalidStopStand-conditionby•Before the START condition and after the STOP condition the device is in standby mode and the SDA line is switched as input with pull-up resistor.

•The control byte that follows the START condition determines the following operation. It

consists of the 5-bit row address, 2 mode control bits and the READ/NWRITE bit that is used to control the direction of the following transfer. A \"0\" defines a write access and a \"1\" a read access.

4552G–4BMCU–09/06

24.7.2Control Byte Format

EEPROM Address

Start

Mode Control BitsC1

Read/ NWriteR/NW

Ackn

StartControl byteAcknData byteAcknData byteAcknStop

24.8EEPROM

The EEPROM has a size of 512 bits and is organized as 32×16-bit matrix. To read and writedata to and from the EEPROM the serial interface must be used. The interface supports one andtwo byte write accesses and one to n-byte read accesses to the EEPROM.

24.8.1

EEPROM – Operating Modes

The operating modes of the EEPROM are defined via the control byte. The control byte containsthe row address, the mode control bits and the read/not-write bit that is used to control the direc-tion of the following transfer. A \"0\" defines a write access and a \"1\" a read access. The fiveaddress bits select one of the 32 rows of the EEPROM memory to be accessed. For allaccesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer mustbe read or overwritten via the serial interface. The two mode control bits C1 and C2 define inwhich order the accesses to the buffer are performed: High byte – low byte or low byte – highbyte. The EEPROM also supports autoincrement and autodecrement read operations. Aftersending the start address with the corresponding mode, consecutive memory cells can be readrow by row without transmission of the row addresses.

Two special control bytes enable the complete initialization of EEPROM with \"0\" or with\"1\".

24.8.2

Write Operations

The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the STARTcondition followed by a write control byte and one or two data bytes from the master. It is com-pleted via the STOP condition from the master after the acknowledge cycle.

The programming cycle consists of an erase cycle (write \"zeros\") and the write cycle (write\"ones\"). Both cycles together take about 10 ms.

24.8.3

Acknowledge Polling

If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM willnot acknowledge until the write cycle is finished. This can be used to detect the end of the writecycle. The master must perform acknowledge polling by sending a start condition followed bythe control byte. If the device is still busy with the write cycle, it will not return an acknowledgeand the master has to generate a stop condition or perform further acknowledge pollingsequences. If the cycle is complete, it returns an acknowledge and the master can proceed withthe next read or write cycle.

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4552G–4BMCU–09/06

ATAR862-4

24.8.4

Write One Data Byte

StartControl byteAData byte 1AStop

24.8.5Write Two Data Bytes

StartControl byteAData byte 1AData byte 2AStop

24.8.6Write Control Byte Only

StartControl byteAStop

24.8.7Write Control Bytes

MSB

Write low byte first

C10

C01

LSBR/NW0

Row address

Byte order

LB(R)

HB(R)

MSB

Write high byte first

C11

C00

LSBR/NW0

Row address

Byte order

HB(R)

LB(R)

A -> acknowledge; HB -> high byte; LB -> low byte; R -> row address

24.8.8

Read Operations

The EEPROM allows byte-, word- and current address read operations. The read operations areinitiated in the same way as write operations. Every read access is initiated by sending theSTART condition followed by the control byte which contains the address and the read mode.When the device has received a read command, it returns an acknowledge, loads the addressedword into the read/write buffer and sends the selected data byte to the master. The master hasto acknowledge the received byte if it wants to proceed the read operation. If two bytes are readout from the buffer the device increments respectively decrements the word address automati-cally and loads the buffer with the next word.

The read mode bits determines if the low or high byte is read first from the buffer and if the wordaddress is incremented or decremented for the next read access. If the memory address limit isreached, the data word address will roll over and the sequential read will continue. The mastercan terminate the read operation after every byte by not responding with an acknowledge (N)and by issuing a stop condition.

4552G–4BMCU–09/06

24.8.9Read One Data Byte

StartControl byteAData byte 1NStop

24.8.10Read Two Data Bytes

StartControl byteAData byte 1AData byte 2NStop

24.8.11Read n Data Bytes

StartControl byteAData byte 1AData byte 2A–Data byte nNStop

24.8.12Read Control Bytes

MSB

Read low byte first, address increment

C10

C01

LSBR/NW1

Row address

Byte orderLB(R)HB(R)LB(R+1)HB(R+1)- - -LB(R+n)HB(R+n)

MSB

Read high byte first, address decrement

C11

C00

LSBR/NW1

Row address

Byte orderHB(R)LB(R)HB(R-1)LB(R-1)- - -HB(R-n)LB(R-n)

A -> acknowledge, N -> no acknowledge; HB -> high byte; LB -> low byte, R -> row address

24.9Initialization After a Reset Condition

The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrol-lers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, itmay be necessary to bring the U505M into a known state independent of its internal reset. Thisis performed by writing:

StartControl byteAData byte 1NStop

to the serial interface. If the U505M acknowledges this sequence it is in a defined state. Maybe itis necessary to perform this sequence twice.

100

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25.Absolute Maximum Ratings: Microcontroller Part

All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD).Voltages are given relative to VSSParametersSupply voltage

Input voltage (on any pin)Output short circuit durationOperating temperature rangeStorage temperature rangeSoldering temperature (t ≤ 10 s)

SymbolVDDVINtshortTambTstgTsld

Value-0.3 to +4.0VSS -0.3 ≤ VIN ≤ VDD +0.3

Indefinite-40 to +125-40 to +130

260

UnitVVs°C°C°C

26.Thermal Resistance

ParameterThermal resistance

SymbolRthJA

Value135

UnitK/W

27.DC Operating Characteristics

VSS = 0 V, Tamb = -40°C to +125°C unless otherwise specified.

ParametersPower Supply

Operating voltage at VDDActive currentCPU active

Power down current (CPU sleep,RC oscillator active,

4-MHz quartz oscillator active)Sleep current (CPU sleep,32-kHz quartz oscillator active4-MHz quartz oscillator inactive)Sleep current (CPU sleep,

32-kHz quartz oscillator inactive4-MHz quartz oscillator inactive)Pin capacitance

fSYSCL = 1 MHzVDD = 1.8 VVDD = 3.0 VfSYSCL = 1 MHzVDD = 1.8 VVDD = 3.0 VVDD = 1.8 VVDD = 3.0 VVDD = 1.8 VVDD = 3.0 VAny pin to VSS

VDDIDD

VPOR

20030040700.40.60.10.37

4.0

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

450

µAµAµAµA

µAµAµAµApF

IPD

1802.3

ISleep

ISleepCL

1.510

101

4552G–4BMCU–09/06

27.DC Operating Characteristics (Continued)

VSS = 0 V, Tamb = -40°C to +125°C unless otherwise specified.

Parameters

Power-on Reset Threshold VoltagePOR threshold voltagePOR threshold voltagePOR hysteresis

Voltage Monitor Threshold VoltageVM high threshold voltageVM high threshold voltageVM middle threshold voltageVM middle threshold voltageVM low threshold voltageVM low threshold voltageExternal Input VoltageVMIVMI

All Bi-directional PortsInput voltage LOWInput voltage HIGHInput LOW current (switched pull-up)Input HIGH current (switched pull-down)Input LOW current (static pull-up)Input LOW current (static pull-down)Input leakage current Input leakage current Output LOW current

VDD = 1.8 to 6.5 VVDD = 1.8 to 6.5 VVDD = 2.0 V,

VDD = 3.0 V, VIL= VSSVDD = 2.0 V,

VDD = 3.0 V, VIH = VDDVDD = 2.0 V

VDD = 3.0 V, VIL= VSSVDD = 2.0 V

VDD = 3.0 V, VIH= VDDVIL= VSSVIH= VDD

VOL = 0.2×VDDVDD = 2.0 VVDD = 3.0 VVOH = 0.8×VDDVDD = 2.0 VVDD = 3.0 V

VILVIHIILIIHIILIIHIILIIHIOL

0.52-0.5-2

1.25-1.2-5

VSS0.8 × VDD-1.4-71.47-14-601460

-4-20420-50-16050160

0.2 × VDDVDD-12-401240-100-3201003201001002.58-2.5-8

VVµAµAµAµAµAµAµAµAnAnAmAmAmAmA

VDD = 3 V, VMS = 1VDD = 3 V, VMS = 0

VVMIVVMI

1.2

1.31.3

1.4

VDD > VM, VMS = 1VDD < VM, VMS = 0VDD > VM, VMS = 1VDD < VM, VMS = 0VDD > VM, VMS = 1VDD < VM, VMS = 0

VMThhVMThhVMThmVMThmVMThlVMThl

1.972.362.75

3.03.02.62.62.22.2

2.42.83.25

VVVVVV

BOT = 1BOT = 0

VPORVPORVPOR

1.61.85

1.72.050

1.82.15

VVmV

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Output HIGH currentNote:

IOH

The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller.

102

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28.AC Characteristics

Supply Voltage VDD = 1.8 V to 4.0 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.

Parameters

Operation Cycle Time

VDD = 1.8 V to 4.0 VTamb = -40°C to +125°CVDD = 2.4 V to 4.0 VTamb = -40°C to +125°C

tSYSCLtSYSCL

500250

40004000

nsns

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

System clock cycle

Timer 2 input Timing Pin T2ITimer 2 input clockTimer 2 input LOW timeTimer 2 input HIGH timeTimer 3 Input Timing Pin T3ITimer 3 input clockTimer 3 input LOW timeTimer 3 input HIGH timeInterrupt Request Input TimingInterrupt request LOW timeInterrupt request HIGH timeExternal System ClockEXSCL at OSC1, ECM = ENEXSCL at OSC1, ECM = DIInput HIGH timeReset TimingPower-on reset timeRC Oscillator 1FrequencyStability

RC Oscillator 2 – External ResistorFrequencyStability

Stabilization time

4-MHz Crystal Oscillator (Operating Range VDD = 2.2 V to 4.0 V)FrequencyStart-up timeStability

Integrated input/output capacitances (mask programmable)

CIN/COUT programmable in steps of 2pF

fXtSQ∆f/fCINCOUT

-1000

102020

MHzmsppmpFpF

Rext = 170 kΩ

VDD = 2.0 V to 4.0 VTamb = -40°C to +105°C

fRcOut2∆f/ftS

±1510

MHz%µs

VDD = 2.0 V to 4.0 VTamb = -40°C to +105°C

fRcOut1∆f/f

3.8

±50

MHz%

VDD > VPOR

tPOR

1.5

Rise/fall time < 10 ns Rise/fall time < 10 ns Rise/fall time < 10 ns

fEXSCLfEXSCLtIH

0.50.020.1

MHzMHzµs

Rise/fall time < 10 ns Rise/fall time < 10 ns

tIRLtIRH

100100

nsns

Rise/fall time < 10 ns Rise/fall time < 10 ns

fT3ItT3ILtT3IH

2tSYSCL2tSYSCL

SYSCL/2

MHznsns

Rise/fall time < 10 ns Rise/fall time < 10 ns

fT2ItT2ILtT2IH

100100

MHznsns

103

4552G–4BMCU–09/06

28.AC Characteristics (Continued)

Supply Voltage VDD = 1.8 V to 4.0 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.

ParametersFrequencyStart-up timeStability

Integrated input/output capacitances (mask programmable)

External 32-kHz Crystal ParametersCrystal frequencySerial resistanceStatic capacitanceDynamic capacitance

External 4-MHz Crystal ParametersCrystal frequencySerial resistanceStatic capacitanceDynamic capacitanceEEPROM

Operating current during erase/write cycleEndurance

Data erase/write cycle timeData retention timePower-up to read operationPower-up to write operationSerial InterfaceSCL clock frequency

fSC_MCL

100

500

kHz

Erase-/write cycles

......Tamb = 105°CFor 16-bit access

......Tamb = 105°C

IWREDEDtDEWtDRtDRtPURtPUW

1001

0.20.2

50000050000

6001000000100000

121300

µACyclesCyclesmsYearsYearsmsms

fXRSC0C1

4.0401.43

1503

MHzWpFfF

fXRSC0C1

32.768301.53

kHzkΩpFfF

CIN/COUT programmable in steps of 2pF

Test Conditions

SymbolfXtSQ∆f/fCINCOUT

-1000Min.

Typ.32.7680.5

102020Max.

UnitkHzsppmpFpF

32-kHz Crystal Oscillator (Operating Range VDD = 2.0 V to 4.0 V)

29.Crystal Characteristics

Figure 29-1.Crystal Equivalent Circuit

EquivalentcircuitOSCINSCLINOSCOUTSCLOUTLC1RSC0104

ATAR862-4

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ATAR862-4

30.Emulation

The basic function of emulation is to test and evaluate the customer's program and hardware inreal time. This therefore enables the analysis of any timing, hardware or software problem. Foremulation purposes, all MARC4 controllers include a special emulation mode. In this mode, theinternal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow anexternal access to the on-chip peripherals. The MARC4 emulator uses this mode to control theperipherals of any MARC4 controller (target chip) and emulates the lost ports for the application.The MARC4 emulator can stop and restart a program at specified points during execution, mak-ing it possible for the applications engineer to view the memory contents and those of variousregisters during program execution. The designer also gains the ability to analyze the executedinstruction sequences and all the I/O activities.

Figure 30-1.MARC4 Emulation

MARC4 emulatorProgrammemory MARC4emulation-CPUI/O busEmulator target boardMARC4 target chipPort 0I/O controlPort 1 TracememoryCORECORE(inactive)PeripheralsPort 0Control logicPort 1Emulation controlSYSCL/TCL,TE, NRSTApplication-specific hardwarePersonal computer105

4552G–4BMCU–09/06

31.Option Settings for Ordering

Please select the option settings from the list below and insert ROM CRC.

Output(1)InputOutputPort 5

InputPort 1BP10[X][][]

CMOSOpen drain [N]Open drain [P]

[][X][][]

Switched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-downSwitched pull-upSwitched pull-downStatic pull-upStatic pull-down

BP50[][][]

CMOSOpen drain [N]Open drain [P]

[][][][]

Recommended settings for pins not available externally(2)

BP13

Recommended settings for pins not available externally(2)Port 2BP20

(3)

[X][][]CMOS

Open drain [N]Open drain [P][][X][][]

[][][][X][][]

CMOS

Open drain [N]Open drain [P]CMOS

Open drain [N]Open drain [P]

BP21

Recommended settings for pins not available externally

BP22

Recommended settings for pins not available externally

BP23

[][][][][][X][][]

BP51

Recommended settings for pins not available externally

BP52

[X][][]CMOS

Open drain [N]Open drain [P][][X][][]

[][][][][][]

CMOS

Open drain [N]Open drain [P]CMOS

Open drain [N]Open drain [P]

BP53

[[[[[[[]]]]]]]

[]

Port 6

[X][][]CMOS

Open drain [N]Open drain [P][][X][][]

BP60

[][][]CMOS

Open drain [N]Open drain [P][][][][]

[][][][][][]

CMOS

Open drain [N]Open drain [P]CMOS

Open drain [N]Open drain [P]

Port 4BP40

[[[[[[]]]]]]

BP63

[][][]CMOS

Open drain [N]Open drain [P]

[[[[]]]]

OSC1

[][]

[][][][]

OSC2

BP41[][][]

CMOSOpen drain [N]Open drain [P]CMOS

Open drain [N]Open drain [P]CMOS

Open drain [N]Open drain [P]

[][[[[[[[[[[[]]]]]]]]]]]

No integrated capacitance

Internal capacitance [ _____pF](Cint = 0 to 20 pF in steps of 0.63pF)No integrated capacitance

Internal capacitance [ _____pF](Cint = 0 to 20 pF in steps of 0.63pF)External resistor

External clock OSC1 or External clock OSC232-kHz crystal4-MHz crystal

Clock Used

BP42

[][][][][][]

[[[[[]]]]]

BP43ECM (External Clock Monitor)

[][]EnableDisable

Approval:Note:

File: Date:

.HEXCRC:

Signature:

HEX1.It is required to select an output option for each port pin (Port 1, Port 4, Port 5, Port 6)

2.It is required to select one of the input options for pons not available externally or to use the recommended settings.3.Do not use external components at BP20 that pull to VSS during reset representing a resistor < 150kΩ.

106

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4552G–4BMCU–09/06

ATAR862-4

32.Ordering Information

Extended Type Number(1)ATAR862x-yyy-TNQYfProgram Memory

4 kB ROM

Data-EEPROM

512 bit

PackageSSO24

DeliveryTaped and reeled

Note:

1.x= Hardware revision

yyy= Customer specific ROM-version and customizingTN= Package (SSO24)

Q= Taped and reeled (4000 pcs)Y= Lead freef= RF operating frequency, 4 means 433 MHz, 3 and 8 or unless customized

33.Package Information

Package SSO245.75.3Dimensions in mm8.054.57.804.31.300.250.150.150.650.056.67.156.32413technical drawingsaccording to DINspecifications1124552G–4BMCU–09/06

107

34.Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.Revision No.4552G-4BMCU-09/06

History

• ESD protection of the “UHF ASK/FSK Transmitter Block” in section 3 on page 4 is transferred to the appropriate product PPAP• Table “Ordering Information” on page 107 changed• Put datasheet in new template

• Page 30: Section “32-kHz Oscillator” changed• Page 107: Ordering Information changed

• Abs. Max. Ratings table (page 11): row “Input voltage” changed• Abs. Max. Ratings table (page 11): table note 1 changed• El. Char. table (page 12): row “PA_ENABLE input“ changed• El. Char. table (page 12): table note 1 changed

4552F-4BMCU-05/06

4552E-4BMCU-09/04

108

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4552G–4BMCU–09/06

ATAR862-4

35.Table of Contents

1234567

Description ...............................................................................................1Pin Configuration .....................................................................................2UHF ASK/FSK Transmitter Block ...........................................................4Features ....................................................................................................4Description ...............................................................................................4General Description .................................................................................6Functional Description ............................................................................6

7.17.27.37.4

ASK Transmission .............................................................................................6FSK Transmission .............................................................................................6CLK Output ........................................................................................................7Application Circuit ..............................................................................................8

Absolute Maximum Ratings: RF Part ...................................................11Thermal Resistance ...............................................................................11

10Electrical Characteristics ......................................................................1111Microcontroller Block ............................................................................1312Features ..................................................................................................1313Description .............................................................................................1314Introduction ............................................................................................1415MARC4 Architecture General Description ...........................................1516Components of MARC4 Core ................................................................15

16.116.216.316.416.516.616.716.816.9

ROM ................................................................................................................16RAM .................................................................................................................16Registers .........................................................................................................17ALU ..................................................................................................................19I/O Bus .............................................................................................................19Instruction Set ..................................................................................................19Interrupt Structure ............................................................................................20Software Interrupts ..........................................................................................22Hardware Interrupts .........................................................................................22

109

4552G–4BMCU–09/06

17Master Reset ...........................................................................................23

17.1

Power-on Reset and Brown-out Detection ......................................................23

18Voltage Monitor ......................................................................................2419Clock Generation ...................................................................................26

19.119.219.3

Clock Module ...................................................................................................26Oscillator Circuits and External Clock Input Stage ..........................................27Clock Management ..........................................................................................30

20Power-down Modes ...............................................................................3121Peripheral Modules ................................................................................32

21.121.221.321.421.521.621.721.821.921.1021.1121.1221.1321.14

Addressing Peripherals ...................................................................................32Bi-directional Ports ..........................................................................................35Bi-directional Port 1 .........................................................................................35Bi-directional Port 2 .........................................................................................36Bi-directional Port 5 .........................................................................................38Bi-directional Port 4 .........................................................................................40Bi-directional Port 6 .........................................................................................41Universal Timer/Counter/ Communication Module (UTCM) ............................42Timer 1 ............................................................................................................43Timer 2 ............................................................................................................47Timer 2 Modes .................................................................................................48Timer 2 Output Modes .....................................................................................50Timer 2 Output Signals ....................................................................................50Timer 2 Registers ............................................................................................53

22Timer 3 ....................................................................................................58

22.122.222.322.422.522.622.722.822.9

Features ..........................................................................................................58Timer/Counter Modes ......................................................................................59Timer 3 Modulator/Demodulator Modes ..........................................................63Timer 3 Modulator for Carrier Frequency Burst Modulation ............................66Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals .............................................................................................................66Timer 3 Registers............................................................................................ 67Timer 3 Capture Register ................................................................................71Synchronous Serial Interface (SSI) .................................................................72Serial Interface Registers ................................................................................80

110

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ATAR862-4

23Combination Modes ...............................................................................83

23.123.223.323.423.523.623.723.823.9

Combination Mode Timer 2 and SSI ...............................................................83Combination Mode Timer 3 and SSI ...............................................................87Combination Mode Timer 2 and Timer 3 .........................................................91Combination Mode Timer 2, Timer 3 and SSI .................................................93Microcontroller Block .......................................................................................95U505M EEPROM ............................................................................................96Serial Interface ................................................................................................97EEPROM .........................................................................................................98Initialization After a Reset Condition ..............................................................100

24Absolute Maximum Ratings: Microcontroller Part ............................10125Thermal Resistance .............................................................................10126DC Operating Characteristics .............................................................10127AC Characteristics ...............................................................................10328Crystal Characteristics ........................................................................10429Emulation ..............................................................................................10530Option Settings for Ordering .............................................................10631Ordering Information ...........................................................................10732Package Information ............................................................................10733Revision History ...................................................................................10834Table of Contents .................................................................................109

111

4552G–4BMCU–09/06

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4552G–4BMCU–09/06

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