DS90CR287/DS90CR288A+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-85MHZOctober1999
DS90CR287/DS90CR288A
+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-85MHZ
GeneralDescription
TheDS90CR287transmitterconverts28bitsofCMOS/TTLdataintofourLVDS(LowVoltageDifferentialSignaling)datastreams.Aphase-lockedtransmitclockistransmittedinpar-allelwiththedatastreamsoverafifthLVDSlink.Everycycleofthetransmitclock28bitsofinputdataaresampledandtransmitted.TheDS90CR288AreceiverconvertsthefourLVDSdatastreamsbackinto28bitsofCMOS/TTLdata.Atatransmitclockfrequencyof85MHZ,28bitsofTTLdataaretransmittedatarateof595MbpsperLVDSdatachannel.Usinga85MHZclock,thedatathroughputis2.38Gbit/s(297.5Mbytes/sec).
ThischipsetisanidealmeanstosolveEMIandcablesizeproblemsassociatedwithwide,highspeedTTLinterfaces.
Features
nnnnnnnnnnnnn
20to85MHZshiftclocksupport
50%dutycycleonreceiveroutputclock
Best–in–ClassSet&HoldTimesonTxINPUTsLowpowerconsumption
±1Vcommonmoderange(around+1.2V)NarrowbusreducescablesizeandcostUpto2.38Gbpsthroughput
Upto297.5Megabytes/secbandwidth
345mV(typ)swingLVDSdevicesforlowEMIPLLrequiresnoexternalcomponentsRisingedgedatastrobe
CompatiblewithTIA/EIA-644LVDSstandardLowprofile56-leadTSSOPpackage
BlockDiagrams
DS90CR287
DS90CR288A
DS101087-1DS101087-27
OrderNumberDS90CR287MTDSeeNSPackageNumberMTD56OrderNumberDS90CR288AMTDSeeNSPackageNumberMTD56
TRI-STATE®isaregisteredtrademarkofNationalSemiconductorCorporation.
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DS90CR287/DS90CR288APinDiagrams
DS90CR287
DS90CR288A
DS101087-21DS101087-22
TypicalApplication
DS101087-23
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DS90CR287/DS90CR288AAbsoluteMaximumRatings(Note1)
IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.SupplyVoltage(VCC)CMOS/TTLInputVoltageCMOS/TTLOutputVoltageLVDSReceiverInputVoltageLVDSDriverOutputVoltage
−0.3Vto+4V−0.5Vto(VCC+
0.3V)
−0.3Vto(VCC+
0.3V)
−0.3Vto(VCC+
0.3V)
−0.3Vto(VCC+
0.3V)
DS90CR288APackageDerating:DS90CR287DS90CR288A
ESDRating
(HBM,1.5kΩ,100pF)(EIAJ,0Ω,200pF)
LatchUpTolerance@+25˚C
1.61W
12.5mW/˚Cabove
+25˚C
12.4mW/˚Cabove
+25˚C
>7kV>700V>±300mA
LVDSOutputShortCircuitDurationContinuousJunctionTemperature+150˚CStorageTemperature−65˚Cto+150˚CLeadTemperature(Soldering,4sec.)+260˚CMaximumPackagePowerDissipation@+25˚CMTD56(TSSOP)Package:DS90CR2871.63W
RecommendedOperating
Conditions
SupplyVoltage(VCC)OperatingFreeAirTemperature(TA)ReceiverInputRange
SupplyNoiseVoltage(VCC)
Min3.0−100
Nom3.3+25
Max3.6+702.4100
UnitsV˚CVmVPPElectricalCharacteristics
OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolVIHVILVOHVOLVCLIINIOSVOD∆VODVOS∆VOSIOSIOZParameter
HighLevelInputVoltageLowLevelInputVoltageHighLevelOutputVoltageLowLevelOutputVoltageInputClampVoltageInputCurrent
OutputShortCircuitCurrentDifferentialOutputVoltageChangeinVODbetween
ComplimentaryOutputStatesOffsetVoltage(Note4)ChangeinVOSbetween
ComplimentaryOutputStatesOutputShortCircuitCurrentOutput
TRI-STATE®
Current
VOUT=0V,RL=100ΩPWRDWN=0V,VOUT=0VorVCCLVDSRECEIVERDCSPECIFICATIONSVTHVTLIINDifferentialInputHighThresholdDifferentialInputLowThresholdInputCurrent
VIN=+2.4V,VCC=3.6VVIN=0V,VCC=3.6VVCM=+1.2V
−100
+100
mVmVµAµA
−3.5
1.125
1.25
IOH=−0.4mAIOL=2mAICL=−18mA
VIN=0.4V,2.5VorVCCVIN=GNDVOUT=0VRL=100Ω
250
LVDSDRIVERDCSPECIFICATIONS
290
450351.37535−5
mVmVVmVmAµA
−10
Conditions
Min2.0GND2.7
3.30.06−0.79+1.80−60
−1200.3−1.5+15
Typ
MaxVCC0.8
Units
VVVVVµAµAmA
CMOS/TTLDCSPECIFICATIONS
±1±10
±10±10
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DS90CR287/DS90CR288AElectricalCharacteristics
SymbolICCTWParameter
TransmitterSupplyCurrentWorstCase(withLoads)
(Continued)
Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified
Conditions
RL=100Ω,CL=5pF,WorstCasePattern
(Figures1,2)
f=33MHzf=40MHzf=66MHzf=85MHz
Min
Typ3132374210
Max4550556055
UnitsmAmAmAmAµA
TRANSMITTERSUPPLYCURRENT
ICCTZTransmitterSupplyCurrentPowerDown
PWRDWN=Low
DriverOutputsinTRI-STATEunderPowerdownModeCL=8pF,WorstCasePattern
(Figures1,3)
f=33MHzf=40MHzf=66MHzf=85MHz
RECEIVERSUPPLYCURRENTICCRWReceiverSupplyCurrentWorstCase
49538196140
7075114135400
mAmAmAmAµA
ICCRZReceiverSupplyCurrentPowerDown
PWRDWN=Low
ReceiverOutputsStayLowduringPowerdownMode
Note1:“AbsoluteMaximumRatings”arethosevaluesbeyondwhichthesafetyofthedevicecannotbeguaranteed.Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.Thetablesof“ElectricalCharacteristics”specifyconditionsfordeviceoperation.
Note2:TypicalvaluesaregivenforVCC=3.3VandTA=+25˚C.
Note3:Currentintodevicepinsisdefinedaspositive.Currentoutofdevicepinsisdefinedasnegative.Voltagesarereferencedtogroundunlessotherwisespeci-fied(exceptVODand∆VOD).
Note4:VOSpreviouslyreferredasVCM.
TransmitterSwitchingCharacteristics
OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolLLHTLHLTTCITTPPos0TPPos1TPPos2TPPos3TPPos4TPPos5TPPos6TCIPTCIHTCILTSTCTHTCTCCDTPLLSTPDDTJIT
Parameter
LVDSLow-to-HighTransitionTime(Figure2)LVDSHigh-to-LowTransitionTime(Figure2)TxCLKINTransitionTime(Figure4)
TransmitterOutputPulsePositionforBit0(Figure15)TransmitterOutputPulsePositionforBit1TransmitterOutputPulsePositionforBit2TransmitterOutputPulsePositionforBit3TransmitterOutputPulsePositionforBit4TransmitterOutputPulsePositionforBit5TransmitterOutputPulsePositionforBit6TxCLKINPeriod(Figure6)TxCLKINHighTime(Figure6)TxCLKINLowTime(Figure6)TxINSetuptoTxCLKIN(Figure6)TxINHoldtoTxCLKIN(Figure6)
TxCLKINtoTxCLKOUTDelay@25˚C,VCC=3.3V(Figure8)TransmitterPhaseLockLoopSet(Figure10)TransmitterPowerdownDelay(Figure13)TxCLKINCycle-toCycleJitter(FigureTBD)
f=85MHzf=85MHz
1.0−0.201.483.164.516.528.209.8811.760.35T0.35T2.503.8
6.3101002
01.683.365.046.728.4010.08T0.5T0.5T
Min
Typ0.750.75
Max1.51.56.00.201.883.565.246.928.6010.28500.65T0.65T
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsmsnsns
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DS90CR287/DS90CR288AReceiverSwitchingCharacteristics
OverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecifiedSymbolCLHTCHLTRSPos0RSPos1RSPos2RSPos3RSPos4RSPos5RSPos6RSKMRCOPRCOHRCOLRSRCRHRCRCCDRPLLSRPDD
Parameter
CMOS/TTLLow-to-HighTransitionTime(Figure3)CMOS/TTLHigh-to-LowTransitionTime(Figure3)ReceiverInputStrobePositionforBit0(Figure16)ReceiverInputStrobePositionforBit1ReceiverInputStrobePositionforBit2ReceiverInputStrobePositionforBit3ReceiverInputStrobePositionforBit4ReceiverInputStrobePositionforBit5ReceiverInputStrobePositionforBit6RxINSkewMargin(Note5)(Figure17)RxCLKOUTPeriod(Figure7)RxCLKOUTHighTime(Figure7)RxCLKOUTLowTime(Figure7)RxOUTSetuptoRxCLKOUT(Figure7)RxOUTHoldtoRxCLKOUT(Figure7)
RxCLKINtoRxCLKOUTDelay@25˚C,VCC=3.3V(Note6)(Figure9)ReceiverPhaseLockLoopSet(Figure11)ReceiverPowerdownDelay(Figure14)
f=85MHzf=85MHzf=85MHz
0.492.173.855.537.218.8910.5729011.7643.53.53.55.5
7
9.5101
T55
506.56
Min
Typ21.80.842.524.205.887.569.2410.92
Max3.53.51.192.874.556.237.919.5911.27
Unitsnsnsnsnsnsnsnsnsnspsnsnsnsnsnsnsmsµs
Note5:ReceiverSkewMarginisdefinedasthevaliddatasamplingregionatthereceiverinputs.Thismargintakesintoaccountthetransmitterpulsepositions(minandmax)andthereceiverinputsetupandholdtime(internaldatasamplingwindow-RSPOS).ThismarginallowsLVDSinterconnectskew,inter-symbolinterference(bothdependentontype/lengthofcable),andsourceclock(lessthan150ps).
Note6:Totallatencyforthechannellinkchipsetisafunctionofclockperiodandgatedelaysthroughthetransmitter(TCCD)andreceiver(RCCD).Thetotallatencyforthe217/287transmitterand218/288Areceiveris:(T+TCCD)+(2*T+RCCD),whereT=Clockperiod.
ACTimingDiagrams
DS101087-2
FIGURE1.“WorstCase”TestPattern
DS101087-3
DS101087-4
FIGURE2.DS90CR287(Transmitter)LVDSOutputLoadandTransitionTimes
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DS90CR287/DS90CR288AACTimingDiagrams
(Continued)
DS101087-5
DS101087-6
FIGURE3.DS90CR288A(Receiver)CMOS/TTLOutputLoadandTransitionTimes
DS101087-7
FIGURE4.DS90CR287(Transmitter)InputClockTransitionTime
DS101087-8
Note7:MeasurementsatVDIFF=0V
Note8:TCCSmeasuredbetweenearliestandlatestLVDSedges.Note9:TxCLKDifferentialLow→HighEdge
FIGURE5.DS90CR287(Transmitter)Channel-to-ChannelSkew
DS101087-9
FIGURE6.DS90CR287(Transmitter)Setup/HoldandHigh/LowTimes
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DS90CR287/DS90CR288AACTimingDiagrams
(Continued)
DS101087-10
FIGURE7.DS90CR288A(Receiver)Setup/HoldandHigh/LowTimes
DS101087-11
FIGURE8.DS90CR287(Transmitter)ClockIntoClockOutDelay
DS101087-12
FIGURE9.DS90CR288A(Receiver)ClockIntoClockOutDelay
DS101087-13
FIGURE10.DS90CR287(Transmitter)PhaseLockLoopSetTime
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DS90CR287/DS90CR288AACTimingDiagrams
(Continued)
DS101087-14
FIGURE11.DS90CR288A(Receiver)PhaseLockLoopSetTime
DS101087-16
FIGURE12.28ParalIeITTLDataInputsMappedtoLVDSOutputs
DS101087-17
FIGURE13.TransmitterPowerdownDeIay
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DS90CR287/DS90CR288AACTimingDiagrams
(Continued)
DS101087-18
FIGURE14.ReceiverPowerdownDelay
DS101087-19
FIGURE15.TransmitterLVDSOutputPulsePositionMeasurement
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DS90CR287/DS90CR288AACTimingDiagrams
(Continued)
DS101087-28
FIGURE16.ReceiverLVDSInputStrobePosition
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DS90CR287/DS90CR288AACTimingDiagrams
(Continued)
DS101087-20
C—SetupandHoldTime(Internaldatasamplingwindow)definedbyRspos(receiverinputstrobeposition)minandmaxTppos—Transmitteroutputpulseposition(minandmax)
RSKM≥CableSkew(type,length)+SourceClockJitter(cycletocycle)(Note10)+ISI(Inter-symbolinterference)(Note11)CableSkew—typically10ps–40psperfoot,mediadependentNote10:Cycle-to-cyclejitterislessthan150psat85MHZ.Note11:ISIisdependentoninterconnectlength;maybezero
FIGURE17.ReceiverLVDSInputSkewMargin
ApplicationsInformation
TheDS90CR287andDS90CR288Aarebackwardcompat-iblewiththeexisting5VChannelLinktransmitter/receiverpair(DS90CR283,DS90CR284).Toupgradefroma5Vtoa3.3Vsystemthefollowingmustbeaddressed:1.
Change5Vpowersupplyto3.3V.ProvidethissupplytotheVCC,LVDSVCCandPLLVCC.
2.3.
Transmitterinputandcontrolinputsexcept3.3VTTL/CMOSlevels.Theyarenot5Vtolerant.
Thereceiverpowerdownfeaturewhenenabledwilllockreceiveroutputtoalogiclow.However,the5V/66MHzreceivermaintaintheoutputsinthepreviousstatewhenpowerdownoccurred.
DS90CR287PinDescription—ChannelLinkTransmitter
PinNameTxINTxOUT+TxOUT−TxCLKINTxCLKOUT+TxCLKOUT−PWRDWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND
I/OIOOIOOIIIIIII
No.28441111451213
TTLlevelinput.
PositiveLVDSdifferentialdataoutput.NegativeLVDSdifferentialdataoutput.
TTLIeveIclockinput.Therisingedgeactsasdatastrobe.PinnameTxCLKIN.PositiveLVDSdifferentialclockoutput.NegativeLVDSdifferentialclockoutput.
TTLlevelinput.Assertion(lowinput)TRI-STATEStheoutputs,ensuringlowcurrentatpowerdown.
PowersupplypinsforTTLinputs.GroundpinsforTTLinputs.PowersupplypinforPLL.GroundpinsforPLL.
PowersupplypinforLVDSoutputs.GroundpinsforLVDSoutputs.
Description
DS90CR288APinDescription—ChannelLinkReceiver
PinNameRxIN+RxIN−RxOUTRxCLKIN+RxCLKIN−RxCLKOUT
I/OIIOIIO
No.4428111
PositiveLVDSdifferentialdatainputs.NegativeLVDSdifferentialdatainputs.TTLleveldataoutputs.
PositiveLVDSdifferentialclockinput.NegativeLVDSdifferentialclockinput.
TTLlevelclockoutput.Therisingedgeactsasdatastrobe.PinnameRxCLKOUT.
Description
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DS90CR287/DS90CR288AApplicationsInformation
PinNamePWRDWNVCCGNDPLLVCCPLLGNDLVDSVCCLVDSGND
I/OIIIIIII
No.1451213
(Continued)
(Continued)
DS90CR288APinDescription—ChannelLinkReceiver
Description
PowersupplypinsforTTLoutputs.GroundpinsforTTLoutputs.PowersupplyforPLL.GroundpinforPLL.
PowersupplypinforLVDSinputs.GroundpinsforLVDSinputs.
TTLlevelinput.Whenasserted(lowinput)thereceiveroutputsarelow.
TheChannelLinkdevicesareintendedtobeusedinawidevarietyofdatatransmissionapplications.Dependingupontheapplicationtheinterconnectingmediamayvary.Forex-ample,forlowerdatarate(clockrate)andshortercablelengths(<2m),themediaelectricalperformanceislesscriti-cal.Forhigherspeed/longdistanceapplicationsthemedia’sperformancebecomesmorecritical.Certaincableconstruc-tionsprovidetighterskew(matchedelectricallengthbe-tweentheconductorsandpairs).Twin-coaxforexample,hasbeendemonstratedatdistancesasgreatasTBDmetersandwiththemaximumdatatransferofTBDGbit/s.Addi-tionalapplicationsinformationcanbefoundinthefollowingNationalInterfaceApplicationNotes:AN=####AN-1041AN-1108AN-806AN-905AN-916
Topic
IntroductiontoChannelLinkChannelLinkPCBandInterconnectDesign-InGuidelinesTransmissionLineTheory
TransmissionLineCalculationsandDifferentialImpedanceCableInformation
cabletype.Thisoverallshieldresultsinimprovedtransmis-sionparameterssuchasfasterattainablespeeds,longerdistancesbetweentransmitterandreceiverandreducedproblemsassociatedwithEMSorEMI.
Thehigh-speedtransportofLVDSsignalshasbeendemon-stratedonseveraltypesofcableswithexcellentresults.However,thebestoverallperformancehasbeenseenwhenusingTwin-Coaxcable.Twin-CoaxhasverylowcableskewandEMIduetoitsconstructionanddoubleshielding.Allofthedesignconsiderationsdiscussedhereandlistedinthesupplementalapplicationnotesprovidethesubsystemcom-municationsdesignerwithmanyusefulguidelines.Itisrec-ommendedthatthedesignerassessthetradeoffsofeachapplicationthoroughlytoarriveatareliableandeconomicalcablesolution.
RECEIVERFAILSAFEFEATURE:Thesereceivershavein-putfailsafebiascircuitrytoguaranteeastablereceiverout-putforfloatingorterminatedreceiverinputs.UndertheseconditionsreceiverinputswillbeinaHIGHstate.Ifaclocksignalispresent,dataoutputswillallbeHIGH;iftheclockin-putisalsofloating/terminated,dataoutputswillremaininthelastvalidstate.Afloating/terminatedclockinputwillresultinaHIGHclockoutput.
BOARDLAYOUT:ToobtainthemaximumbenefitfromthenoiseandEMIreductionsofLVDS,attentionshouldbepaidtothelayoutofdifferentiallines.Linesofadifferentialpairshouldalwaysbeadjacenttoeliminatenoiseinterferencefromothersignalsandtakefulladvantageofthenoisecan-celingofthedifferentialsignals.Theboarddesignershouldalsotrytomaintainequallengthonsignaltracesforagivendifferentialpair.Aswithanyhighspeeddesign,theimped-ancediscontinuitiesshouldbelimited(reducethenumbersofviasandno90degreeanglesontraces).Anydiscontinui-tieswhichdooccurononesignallineshouldbemirroredintheotherlineofthedifferentialpair.Careshouldbetakentoensurethatthedifferentialtraceimpedancematchthediffer-entialimpedanceoftheselectedphysicalmedia(thisimped-anceshouldalsomatchthevalueoftheterminationresistorthatisconnectedacrossthedifferentialpairatthereceiver’sinput).Finally,thelocationoftheCHANNELLINKTxOUT/RxINpinsshouldbeascloseaspossibletotheboardedgesoastoeliminateexcessivepcbruns.Alloftheseconsider-ationswilllimitreflectionsandcrosstalkwhichadverselyef-fecthighfrequencyperformanceandEMI.
UNUSEDINPUTS:AllunusedinputsattheTxINinputsofthetransmittermaybetiedtogroundorleftnoconnect.AllunusedoutputsattheRxOUToutputsofthereceivermustthenbeleftfloating.
TERMINATION:Useofcurrentmodedriversrequiresater-minatingresistoracrossthereceiverinputs.TheCHANNEL
12
CABLES:Acableinterfacebetweenthetransmitterandre-ceiverneedstosupportthedifferentialLVDSpairs.The21-bitCHANNELLINKchipset(DS90CR217/218A)requiresfourpairsofsignalwiresandthe28-bitCHANNELLINKchipset(DS90CR287/288A)requiresfivepairsofsignalwires.Theidealcable/connectorinterfacewouldhaveacon-stant100Ωdifferentialimpedancethroughoutthepath.Itisalsorecommendedthatcableskewremainbelow140ps(85MHZclockrate)tomaintainasufficientdatasamplingwin-dowatthereceiver.
Inadditiontothefourorfivecablepairsthatcarrydataandclock,itisrecommendedtoprovideatleastoneadditionalconductor(orpair)whichconnectsgroundbetweenthetransmitterandreceiver.Thislowimpedancegroundpro-videsacommonmodereturnpathforthetwodevices.Someofthemorecommonlyusedcabletypesforpoint-to-pointap-plicationsincludeflatribbon,flex,twistedpairandTwin-Coax.Allareavailableinavarietyofconfigurationsandop-tions.Flatribboncable,flexandtwistedpairgenerallyperformwellinshortpoint-to-pointapplicationswhileTwin-Coaxisgoodforshortandlongapplications.Whenusingrib-boncable,itisrecommendedtoplaceagroundlinebetweeneachdifferentialpairtoactasabarriertonoisecouplingbe-tweenadjacentpairs.ForTwin-Coaxcableapplications,itisrecommendedtoutilizeashieldoneachcablepair.Allex-tendedpoint-to-pointapplicationsshouldalsoemployanoverallshieldsurroundingallcablepairsregardlessofthe
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DS90CR287/DS90CR288AApplicationsInformation
(Continued)
LINKchipsetwillnormallyrequireasingle100Ωresistorbe-tweenthetrueandcomplementlinesoneachdifferentialpairofthereceiverinput.Theactualvalueoftheterminationresistorshouldbeselectedtomatchthedifferentialmodecharacteristicimpedance(90Ωto120Ωtypical)ofthecable.Figure18showsanexample.Noadditionalpull-uporpull-downresistorsarenecessaryaswithsomeotherdifferentialtechnologiessuchasPECL.Surfacemountresistorsarerecommendedtoavoidtheadditionalinductancethatac-companiesleadedresistors.Theseresistorsshouldbeplacedascloseaspossibletothereceiverinputpinstore-ducestubsandeffectivelyterminatethedifferentiallines.
DECOUPLINGCAPACITORS:Bypassingcapacitorsareneededtoreducetheimpactofswitchingnoisewhichcouldlimitperformance.Foraconservativeapproachthreeparallel-connecteddecouplingcapacitors(Multi-LayeredCe-ramictypeinsurfacemountformfactor)betweeneachVCCandthegroundplane(s)arerecommended.Thethreeca-pacitorvaluesare0.1µF,0.01µFand0.001µF.AnexampleisshowninFigure19.Thedesignershouldemploywidetracesforpowerandgroundandensureeachcapacitorhasitsownviatothegroundplane.Ifboardspaceislimitingthenumberofbypasscapacitors,thePLLVCCshouldreceivethemostfiltering/bypassing.NextwouldbetheLVDSVCCpinsandfinallythelogicVCCpins.
DS101087-24
FIGURE18.LVDSSerializedLinkTermination
creatingalowjitterLVDSclock.Thesemeasuresprovidemoremarginforchannel-to-channelskewandinterconnectskewasapartoftheoveralljitter/skewbudget.
COMMONMODEvs.DIFFERENTIALMODENOISEMAR-GIN:ThetypicalsignalswingforLVDSis300mVcenteredat+1.2V.TheCHANNELLINKreceiversupportsa100mVthresholdthereforeprovidingapproximately200mVofdiffer-entialnoisemargin.Commonmodeprotectionisofmoreim-portancetothesystem’soperationduetothedifferentialdatatransmission.LVDSsupportsaninputvoltagerangeofGroundto+2.4V.Thisallowsfora±1.0Vshiftingofthecen-terpointduetogroundpotentialdifferencesandcommonmodenoise.
POWERSEQUENCINGANDPOWERDOWNMODE:Out-putsoftheCNANNELLINKtransmitterremaininTRI-STATE®untilthepowersupplyreaches2V.Clockanddataoutputswillbegintotoggle10msafterVCChasreached3VandthePowerdownpinisabove1.5V.EitherdevicemaybeplacedintoapowerdownmodeatanytimebyassertingthePowerdownpin(activelow).Totalpowerdissipationforeachdevicewilldecreaseto5µW(typical).
TheCHANNELLINKchipsetisdesignedtoprotectitselffromaccidentallossofpowertoeitherthetransmitterorre-ceiver.Ifpowertothetransmitboardislost,thereceiverclocks(inputandoutput)stop.Thedataoutputs(RxOUT)re-tainthestatestheywereinwhentheclocksstopped.Whenthereceiverboardlosespower,thereceiverinputsareshortedtoVCCthroughaninternaldiode.Currentislimited(5mAperinput)bythefixedcurrentmodedrivers,thusavoidingthepotentialforlatchupwhenpoweringthedevice.
DS101087-25
FIGURE19.CHANNELLINKDecouplingConfiguration
CLOCKJITTER:TheCHANNELLINKdevicesemployaPLLtogenerateandrecovertheclocktransmittedacrosstheLVDSinterface.ThewidthofeachbitintheserializedLVDSdatastreamisone-sevenththeclockperiod.Forexample,a85MHZclockhasaperiodof11.76nswhichresultsinadatabitwidthof1.68ns.Differentialskew(∆twithinonedif-ferentialpair),interconnectskew(∆tofonedifferentialpairtoanother)andclockjitterwillallreducetheavailablewindowforsamplingtheLVDSserialdatastreams.Caremustbetakentoensurethattheclockinputtothetransmitterbeacleanlownoisesignal.IndividualbypassingofeachVCCtogroundwillminimizethenoisepassedontothePLL,thus
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DS90CR287/DS90CR288AApplicationsInformation
(Continued)
DS101087-26
FIGURE20.Single-EndedandDifferentialWaveforms
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DS90CR287/DS90CR288A+3.3VRisingEdgeDataStrobeLVDS28-BitChannelLink-85MHZPhysicalDimensions
inches(millimeters)unlessotherwisenoted
OrderNumberDS90CR287MTDorDS90CR288AMTD
DimensionsinmillimetersonlyNSPackageNumberMTD56
LIFESUPPORTPOLICY
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