简易数字秒表的设计
一、实验目的
1、设计一个显示范围为24小时60分钟60秒的简易数字秒表。 2、掌握动态扫描电路的设计方法。
二、实验原理
1、能进行正常的时、分、秒计时功能，分别由6个数码管显示24小时、60分钟、60秒钟的计数器显示。
2、能利用实验系统上的按键实现“校时”“校分”功能： 错误！未找到引用源。按下“SA”键时，计时器迅速递增，并按24小时循环，计满23小时后回“00”； 错误！未找到引用源。按下“SB”键时，计分器迅速递增，并按59分钟循环，计满59分钟后回“00”，
但不向“时”进位；
错误！未找到引用源。按下“SC”键时，秒清零； 错误！未找到引用源。要求按下“SA”、“SB”或“SC”时均不产生数字跳变（SA”、“SB”、“SC”按
键是有抖动的，必须对其消除抖动处理）。
3、能利用扬声器做整点报时：
错误！未找到引用源。当计时到达59分50秒时开始报时，在59分50秒、52秒、54秒、56秒、
58秒鸣叫，鸣叫声频率可定为500Hz；
错误！未找到引用源。到达59分60秒时为最后一声整点报时，整点报时频率可定为1KHz。
三、实验内容
1、用VHDL语言编程设计简易数字秒表（VHDL程序代码可附在实验报告后面）。 2、锁定引脚并下载验证结果。
四、实验结果
1、画出仿真波形图。 （1）顶层电路波形图
（2）时钟计时波形图
（3）整点报时波形图
（4）分频器波形图
（5）译码显示波形图
2、简单描述你设计的电路下载到试验箱上的结果。（手写）
五、实验小结（手写）
评价项目 所得分数 报告完整正确 □3分 □2分 □1分 其它： 分 程序正确 □3分 □2分 □1分 其它： 分 结果正确 □4分 □3分 □2分 其它： 分 总分： 分 日期： 年 月 日 签名：
顶层原理图：
时钟计时模块原理图：
分频器程序代码： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY syclk IS --对1KHz分频 PORT(clk_1K: IN STD_LOGIC; clk_10H:OUT STD_LOGIC; --10Hz clk_1H:OUT STD_LOGIC; --1Hz clk_500H:OUT STD_LOGIC --500Hz );
END ENTITY syclk;
ARCHITECTURE struct OF syclk IS SIGNAL clktemp1 : STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ; SIGNAL clktemp2 : STD_LOGIC_VECTOR( 2 DOWNTO 0 ) ; SIGNAL clk_10H_temp: STD_LOGIC; SIGNAL clk_1H_temp: STD_LOGIC; SIGNAL clk_500H_temp: STD_LOGIC; BEGIN clk_10H <= clk_10H_temp; clk_500H <= clk_500H_temp; clk_1H <=clk_1H_temp; p1:PROCESS(clk_1K) BEGIN IF ( clk_1K'EVENT AND clk_1K='1' ) THEN IF ( clktemp1 = \"00110001\" ) THEN clktemp1 <= \"00000000\"; clk_10H_temp <= not clk_10H_temp; ELSE clktemp1 <= clktemp1 + '1'; END IF ; clk_500H_temp <= not clk_500H_temp; END IF ; END PROCESS p1; p2:PROCESS(clk_10H_temp) BEGIN IF ( clk_10H_temp'EVENT AND clk_10H_temp='1' ) THEN IF ( clktemp2 = \"100\" ) THEN clktemp2 <= \"000\"; clk_1H_temp <= not clk_1H_temp; ELSE clktemp2 <= clktemp2 + '1'; END IF ; END IF ; END PROCESS p2;
END ARCHITECTURE struct;
译码显示程序代码： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD_LED IS PORT(CLK: IN STD_LOGIC; BCD1,BCD2,BCD3,BCD4,BCD5,BCD6: IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ); LED:OUT STD_LOGIC_VECTOR( 6 DOWNTO 0 ); BIT:OUT STD_LOGIC_VECTOR( 5 DOWNTO 0 )
);
END ENTITY BCD_LED;
ARCHITECTURE struct OF BCD_LED IS SIGNAL CNT6:INTEGER RANGE 0 TO 5 ;
SIGNAL A:STD_LOGIC_VECTOR( 3 DOWNTO 0 ); BEGIN P1:PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN IF CNT6>=5 THEN CNT6<=0; ELSE CNT6 <= CNT6+1; END IF; END IF; END PROCESS P1; P2:PROCESS(CNT6) BEGIN CASE CNT6 IS WHEN 0 =>BIT <= \"000001\";A <= BCD1; WHEN 1 =>BIT <= \"000010\";A <= BCD2; WHEN 2 =>BIT <= \"000100\";A <= BCD3; WHEN 3 =>BIT <= \"001000\";A <= BCD4; WHEN 4 =>BIT <= \"010000\";A <= BCD5; WHEN 5 =>BIT <= \"100000\";A <= BCD6; WHEN OTHERS => NULL; END CASE; END PROCESS P2; P3:PROCESS(A) BEGIN CASE A IS WHEN \"0000\" => LED <= \"1111110\" ; WHEN \"0001\" => LED <= \"0110000\" ; WHEN \"0010\" => LED <= \"1101101\" ; WHEN \"0011\" => LED <= \"1111001\" ; WHEN \"0100\" => LED <= \"0110011\" ; WHEN \"0101\" => LED <= \"1011011\" ; WHEN \"0110\" => LED <= \"1011111\" ; WHEN \"0111\" => LED <= \"1110000\" ; WHEN \"1000\" => LED <= \"1111111\" ; WHEN \"1001\" => LED <= \"1111011\" ; WHEN OTHERS => NULL ; END CASE ; END PROCESS P3; END ARCHITECTURE struct;
整点报时程序代码：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY speek IS PORT(clk_500H:IN STD_LOGIC; clk_1K:IN STD_LOGIC; miaoL:IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ); miaoH:IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ); fenL:IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ); fenH:IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ); speek_out: OUT STD_LOGIC );
END ENTITY speek;
ARCHITECTURE struct OF speek IS BEGIN
speek_out <= clk_500H WHEN ((fenH = \"0101\") AND (fenL = \"1001\") AND (miaoH = \"0101\") AND (miaoL(0) = '0')) ELSE --59分50秒、秒个位为偶数 clk_1K WHEN ((fenH = \"0000\") AND (fenL = \"0000\") AND (miaoH = \"0000\") AND (miaoL = \"0000\")) ELSE '0';
END ARCHITECTURE struct;
D触发器程序代码： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCFQ IS PORT(clk:IN STD_LOGIC; QI :IN STD_LOGIC; QO :OUT STD_LOGIC );
END ENTITY DCFQ;
ARCHITECTURE struct OF DCFQ IS BEGIN PROCESS(CLK) BEGIN IF (clk'EVENT AND clk='1') THEN QO<=QI; END IF ; END PROCESS;
END ARCHITECTURE struct;
十进制计数器程序代码： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cuont10 IS PORT(clk:IN STD_LOGIC; clr:IN STD_LOGIC; cy:OUT STD_LOGIC; data:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ) );
END ENTITY cuont10;
ARCHITECTURE struct OF cuont10 IS SIGNAL data_temp : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); BEGIN data <= data_temp; PROCESS(clk) BEGIN IF ( clr = '1' ) THEN data_temp <= \"0000\"; ELSIF ( clk'EVENT AND clk='1' ) THEN IF ( data_temp = \"1001\" ) THEN -- 二选择的IF语句 data_temp <= \"0000\"; cy <= '1'; ELSE data_temp <= data_temp + '1'; cy <= '0'; END IF ; END IF ; END PROCESS; END ARCHITECTURE struct;
六进制计数器程序代码： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cuont6 IS PORT(clk:IN STD_LOGIC; clr:IN STD_LOGIC; cy:OUT STD_LOGIC; data:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ) );
END ENTITY cuont6;
ARCHITECTURE struct OF cuont6 IS SIGNAL data_temp : STD_LOGIC_VECTOR( 3 DOWNTO 0 ) ; BEGIN data <= data_temp; PROCESS(clk) BEGIN IF ( clr = '1' ) THEN data_temp <= \"0000\"; ELSIF ( clk'EVENT AND clk='1' ) THEN IF ( data_temp = \"0101\" ) THEN data_temp <= \"0000\"; cy <= '1'; ELSE data_temp <= data_temp + '1'; cy <= '0'; END IF ; END IF ; END PROCESS; END ARCHITECTURE struct;
时钟小时计数器： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shi IS--小时 PORT(clk:IN STD_LOGIC; shiL:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); shiH:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ) );
END ENTITY shi;
ARCHITECTURE struct OF shi IS SIGNAL L_temp : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL H_temp : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL cy: STD_LOGIC; BEGIN shiL <= L_temp; shiH <= H_temp; p1:PROCESS(clk) BEGIN IF ( clk'EVENT AND clk='1' ) THEN --如果小时数低位显示9或者显示23，则清0 IF((L_temp=\"1001\")OR((L_temp=\"0011\")AND( H_temp=\"0010\"))) THEN L_temp <= \"0000\"; cy <= '1';
ELSE L_temp <= L_temp + '1'; cy <= '0'; END IF ; END IF ; END PROCESS p1; p2:PROCESS(cy) BEGIN IF ( cy'EVENT AND cy ='1' ) THEN IF ( H_temp = \"0010\" ) THEN H_temp <= \"0000\"; ELSE H_temp <= H_temp + '1'; END IF ; END IF ; END PROCESS p2; END ARCHITECTURE struct;
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