ADS5520www.ti.com.......................................................................................................................................................SBAS310F–MAY2004–REVISEDOCTOBER2008
12-Bit,125MSPSAnalog-To-DigitalConverter
FEATURES
12-BitResolution
125MSPSSampleRate
HighSNR:69.7dBFSat100MHzfINHighSFDR:82dBcat100MHzfIN2.3-VPPDifferentialInputVoltageInternalVoltageReference3.3-VSingle-SupplyVoltage
AnalogPowerDissipation:578mWSerialProgrammingInterfaceTQFP-64PowerPAD™PackageRecommendedOpAmps:
THS3201,THS3202,THS4503,THS4509,
•
THS9001,OPA695,OPA847
•••••••••••
APPLICATIONS
WirelessCommunication
–CommunicationReceivers–BaseStationInfrastructure
TestandMeasurementInstrumentationSingleandMultichannelDigitalReceiversCommunicationInstrumentation–Radar–Infrared
VideoandImagingMedicalEquipment
•••
••
DESCRIPTION
TheADS5520isahigh-performance,12-Bit,125MSPSanalog-to-digitalconverter(ADC).Toprovideacompleteconvertersolution,itincludesahigh-bandwidthlinearsample-and-holdstage(S&H)andinternalreference.Designedforapplicationsdemandingthehighestspeedandhighestdynamicperformanceinlittlespace,theADS5520hasexcellentpowerconsumptionof578mWat3.3-Vsingle-supplyvoltage.Thisallowsanevenhighersystemintegrationdensity.Theprovidedinternalreferencesimplifiessystemdesignrequirements.ParallelCMOS-compatibleoutputensuresseamlessinterfacingwithcommonlogic.
TheADS5520isavailableina64-pinTQFPPowerPADpackageovertheindustrialtemperaturerange.
Table1.ADS5500ProductFamily
80MSPS
12Bit14Bit
ADS5522ADS5542
105MSPSADS5521ADS5541
125MSPSADS5520ADS5500
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PowerPADisatrademarkofTexasInstruments.
Copyright©2004–2008,TexasInstrumentsIncorporated
PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
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ADS5520SBAS310F–MAY2004–REVISEDOCTOBER2008.......................................................................................................................................................www.ti.com
AVDDDRVDDCLK+CLK−
Timing CircuitryCLKOUTVIN+
S&HVIN−
12-BitPipelineADC CoreDigitalErrorCorrectionOutputControlD0...D11OVRDFSCM
InternalReferenceControl LogicSerial Programming RegisterADS5520SENSDATASCLKDRGND
ThisintegratedcircuitcanbedamagedbyESD.TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
AGND
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
ORDERINGINFORMATION(1)
PRODUCTADS5520(1)(2)
PACKAGE-LEADHTQFP-64(2)PowerPAD
PACKAGEDESIGNATOR
PAP
SPECIFIEDTEMPERATURE
RANGE–40°Cto85°C
PACKAGEMARKINGADS5520I
ORDERINGNUMBERADS5520IPAPADS5520IPAPR
TRANSPORTMEDIA,QUANTITY
Tray,160TapeandReel,1000
Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdatasheet.
Thermalpadsize:3,5mmx3,5mm(min),4mmx4mm(max).θJA=21.47°C/WandθJC=2.99°C/W,whenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandard,four-layer,3inx3inPCB.
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ADS5520www.ti.com.......................................................................................................................................................SBAS310F–MAY2004–REVISEDOCTOBER2008
ABSOLUTEMAXIMUMRATINGS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
ADS5520
SupplyVoltage
AnaloginputtoAGND(2)(3)LogicinputtoDRGND
DigitaldataoutputtoDRGNDOperatingtemperaturerangeJunctiontemperatureStoragetemperaturerange(1)(2)(3)
AVDDtoAGND,DRVDDtoDRGNDAGNDtoDRGND
–0.3to3.7±0.1
–0.3tominimum(AVDD+0.3,3.6)
–0.3toDRVDD–0.3toDRVDD
–40to85105–65to150
UNITVVVVV°C°C°C
Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmaydegradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthosespecifiedisnotimplied.
Iftheinputsignalcanexceed3.6V,thenaresistorgreaterthanorequalto25Ωshouldbeaddedinserieswitheachoftheanalog
inputpinstosupportinputvoltagesupto3.8V.Forinputvoltagesabove3.8V,thedevicecanonlyhandletransientsandthedutycycleoftheovershootshouldbelimitedtolessthan5%forinputsupto3.9V.
Theovershootdutycyclecanbedefinedastheratioofthetotaltimeofovershoottothetotalintendeddevicelifetime,expressedasapercentage.Thetotaltimeofovershootistheintegratedtimeofallovershootoccurrencesoverthelifetimeofthedevice.
RECOMMENDEDOPERATINGCONDITIONS
PARAMETERSupplies
Analogsupplyvoltage,AVDD
Outputdriversupplyvoltage,DRVDDAnaloginputDifferentialinputrange
Inputcommon-modevoltage,VCM(1)DigitalOutputMaximumoutputloadClockInput
ADCLKinputsamplerate(sinewave)1/tCClockamplitude,sinewave,differential(2)Clockdutycycle(3)
Openfree-airtemperaturerange
ADS5520I
–40
DLLONDLLOFF
6021
350%
85
°C
12580
MSPSVPP
10
pF
1.45
2.31.55
1.65
VPPV
33
3.33.3
3.63.6
VV
MIN
TYP
MAX
UNIT
(1)(2)(3)Inputcommon-modeshouldbeconnectedtoCM.SeeFigure49formoreinformation.SeeFigure48formoreinformation.
ELECTRICALCHARACTERISTICS
TypicalvaluesgivenatTA=25°C,minandmaxspecifiedoverthefullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,samplingrate=125MSPS,50%clockdutycycle,DLLOn,3-VPPdifferentialclock,and–1dBFSdifferentialinput,unlessotherwisenoted
PARAMETERResolutionAnalogInputsDifferentialinputrangeDifferentialinputimpedanceDifferentialinputcapacitanceAnaloginputcommon-modecurrent(perinput)AnaloginputbandwidthSourceimpedance=50ΩSeeFigure39SeeFigure392.36.64300750VPPkΩpFµAMHzCONDITIONSMINTYP12MAXUNITBitsCopyright©2004–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback
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ADS5520SBAS310F–MAY2004–REVISEDOCTOBER2008.......................................................................................................................................................www.ti.com
ELECTRICALCHARACTERISTICS(continued)
TypicalvaluesgivenatTA=25°C,minandmaxspecifiedoverthefullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,samplingrate=125MSPS,50%clockdutycycle,DLLOn,3-VPPdifferentialclock,and–1dBFSdifferentialinput,unlessotherwisenoted
PARAMETER
VoltageoverloadrecoverytimeInternalReferenceVoltagesReferencebottomvoltage,VREFMReferencetopvoltage,VREFPReferenceerror
Common-modevoltageoutput,VCM
DynamicDCCharacteristicsandAccuracyNomissingcodes
Differentialnonlinearityerror,DNLIntegralnonlinearityerror,INLOffseterror
Offsettemperaturecoefficient
DCpower-supplyrejectionratio,DCPSRRGainerror
(1)
CONDITIONSMINTYP4
MAXUNITClockcyclesVV
0.952.1
–4%
±0.9%1.55±0.05Tested
fIN=10MHzfIN=10MHz
-0.5-1.5–11
Δoffseterror/ΔAVDDfromAVDD=3VtoAVDD=3.6V
–2
±0.25±0.8±1.50.010.25±0.450.01
25°C
Fulltemprange25°C
Fulltemprange
68666866
70.269.370.170.168.869.769.368.40.32
79767875
858479
25°C
Fulltemprange
8382827874
25°C
Fulltemprange25°C
Fulltemprange
79767875
9186848783847874
20.51.5114%
V
LSBLSBmVmV/°CmV/V%FSΔ%/°C
GaintemperaturecoefficientDynamicACCharacteristics
fIN=10MHzfIN=55MHz
Signal-to-noiseratio.SNR
fIN=70MHzfIN=100MHzfIN=150MHzfIN=220MHz
RMSidlechannelnoise
Inputstiedtocommon-modefIN=10MHzfIN=55MHz
Spurious-freedynamicrange,SFDR
fIN=70MHzfIN=100MHzfIN=150MHzfIN=220MHzfIN=10MHzfIN=55MHz
Second-harmonic,HD2
fIN=70MHzfIN=100MHzfIN=150MHzfIN=220MHz
(1)4
Gainerrorisspecifiedbydesignandcharacterization;itisnottestedinproduction.
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25°C
Fulltemprange
dBFS
LSB
dBc
dBc
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ADS5520www.ti.com.......................................................................................................................................................SBAS310F–MAY2004–REVISEDOCTOBER2008
ELECTRICALCHARACTERISTICS(continued)
TypicalvaluesgivenatTA=25°C,minandmaxspecifiedoverthefullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,samplingrate=125MSPS,50%clockdutycycle,DLLOn,3-VPPdifferentialclock,and–1dBFSdifferentialinput,unlessotherwisenoted
PARAMETER
fIN=10MHzfIN=55MHz
Third-harmonic,HD3
fIN=70MHzfIN=100MHzfIN=150MHzfIN=220MHz
Worst-harmonic/spur(otherthanHD2andHD3)
fIN=10MHzfIN=70MHzfIN=10MHzfIN=55MHz
Signal-to-noise+distortion,SINAD
fIN=70MHzfIN=100MHzfIN=150MHzfIN=220MHzfIN=10MHzfIN=55MHz
Totalharmonicdistortion,THD
fIN=70MHzfIN=100MHzfIN=150MHzfIN=220MHz
Effectivenumberofbits,ENOB
Two-toneintermodulationdistortion,IMDACpowersupplyrejectionratio,ACPSRRPowerSupply
Totalsupplycurrent,ICCAnalogsupplycurrent,IAVDDOutputbuffersupplycurrent,IDRVDDPowerdissipationStandbypower
fIN=70MHzfIN=70MHzfIN=70MHzAnalogonly
Outputbufferpowerwith10-pFloadondigitaloutputtogroundWithClocksrunning
23617561578202180
26019070627231250
mWmWmAmAmA
fIN=70MHz
f=10.1MHz,15.1MHz(-7dBFSeachtone)f=50.1MHz,55.1MHz(-7dBFSeachtone)f=148.1MHz,153.1MHz(-7dBFSeachtone)Supplynoisefrequency≤100MHz
25°C
Fulltemprange
7774
25°C
Fulltemprange
7875
25°C
Fulltemprange
67.565.5
25°C25°C25°C
Fulltemprange
67.565.5
25°C
Fulltemprange
7875
CONDITIONS
25°C
Fulltemprange
MIN7976
TYP8988798582828078888669.86969.569.968.669.568.566.78583778179.579757211.3959293.535
dBdBFSBitsdBcdBFSdBcdBc
MAX
UNIT
DIGITALCHARACTERISTICS
Validoverfullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,unlessotherwisenoted
PARAMETER
DigitalInputs
CONDITIONS
MIN
TYP
MAX
UNIT
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ADS5520SBAS310F–MAY2004–REVISEDOCTOBER2008.......................................................................................................................................................www.ti.com
DIGITALCHARACTERISTICS(continued)
Validoverfullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,unlessotherwisenoted
PARAMETER
High-levelinputvoltage,VIHLow-levelinputvoltage,VILHigh-levelinputcurrent,IIHLow-levelinputcurrent,IILInputcurrentforRESETInputcapacitanceDigitalOutputs
Low-leveloutputvoltage,VOLHigh-leveloutputvoltage,VOHOutputcapacitance
CLOAD=10pFCLOAD=10pF
2.8
0.333
0.4
VVpF
–204
CONDITIONS
MIN2.4
0.810–10
TYP
MAX
UNITVVµAµAµApF
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ADS5520www.ti.com.......................................................................................................................................................SBAS310F–MAY2004–REVISEDOCTOBER2008
TIMINGCHARACTERISTICS(1)(2)
TypicalvaluesgivenatTA=25°C,minandmaxspecifiedoverthefullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,samplingrate=125MSPS,50%clockdutycycle,3-VPPdifferentialclock,andCLOAD=10pF,unlessotherwisenoted
PARAMETER
SwitchingSpecificationAperturedelay,tA
Aperturejitter(uncertainty)Datasetuptime,tSUDataholdtime,tH
Inputclocktooutputdatavalidstart,tSTART(4)(5)
Inputclocktooutputdatavalidend,tEND(4)(5)
Outputclockjitter,tJITOutputclockrisetime,trOutputclockfalltime,tf
Inputclocktooutputclockdelay,tPDIDatarisetime,trDatafalltime,tf
Outputenable(OE)todataoutputdelay
InputCLKfallingedgetodatasamplingpointUncertaintyinsamplinginstant
Datavalid(3)to50%ofCLKOUTrisingedge50%ofCLKOUTrisingedgetodatabecominginvalid(3)
InputclockrisingedgetodatavalidstartdelayInputclockrisingedgetodatavalidenddelayUncertaintyinCLKOUTrisingedge,peak-to-peakRisetimeofCLKOUTfrom20%to80%ofDRVDDFalltimeofCLKOUTfrom80%to20%ofDRVDDInputclockrisingedge,zerocrossing,tooutputclockrisingedge50%
Datarisetimemeasuredfrom20%to80%ofDRVDD
Datafalltimemeasuredfrom80%to20%ofDRVDD
Timerequiredforoutputstohavestabletimingswithregardtoinputclock(6)afterOEisactivatedTimetovaliddataaftercomingoutofsoftwarepowerdown
Timetovaliddataafterstoppingandrestartingtheclock
TimeforasampletopropagatetotheADCoutputs
17.5
4.25.82.31.7
13002.7226.91501.71.54.83.62.8
2101.91.75.54.63.7100010001000
ClockcyclesClockcycles2.6
nsfsnsnsnsnspsPPnsnsnsnsnsClockcycles
DESCRIPTION
MIN
TYP
MAX
UNIT
Wake-uptime
Latency(1)(2)(3)(4)(5)(6)
Timingparametersareensuredbydesignandcharacterization,andnottestedinproduction.
SeeTable6throughTable9intheApplicationInformationsectionfortiminginformationatadditionalsamplingfrequencies.Datavalidrefersto2VforLOGICHIGHand0.8VforLOGICLOW.
SeetheOutputInformationsectionfordetailsonusingtheinputclockfordatacapture.
ThesespecificationsapplywhentheCLKOUTpolarityissettorisingedge(accordingtoTable3).Add1/2clockperiodforthevalidnumberforafallingedgeCLKOUTpolarity.
DataoutputsareavailablewithinaclockfromassertionofOE;however,ittakes1000clockcyclestoensurestabletimingwithrespecttoinputclock.
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ADS5520SBAS310F–MAY2004–REVISEDOCTOBER2008.......................................................................................................................................................www.ti.com
AnalogInputSignal
SampleNN+1N+2N+3N+4N+14N+15N+16N+17tAInputClockOutput Clock
tSTARTtPDItsuData Out(D0−D11)
N − 17N − 16N − 15N − 14N − 13N − 3N − 2N − 1NtENDData Invalid17.5 Clock CyclesthA.
ItisrecommendedthattheloadingatCLKOUTandalldatalinesareaccuratelymatchedtoensurethattheabovetimingmatchescloselywiththespecifiedvalues.
Figure1.TimingDiagram
RESETTIMINGCHARACTERISTICS
TypicalvaluesgivenatTA=25°C,minandmaxspecifiedoverthefullrecommendedoperatingtemperaturerange,AVDD=DRVDD=3.3V,and3-VPPdifferentialclock,unlessotherwisenoted
PARAMETER
SwitchingSpecificationPower-ondelay,t1Resetpulsewidth,t2Registerwritedelay,t3Power-uptime
Delayfrompower-onofAVDDandDRVDDtoRESETpulseactivePulsewidthofactiveRESETsignalDelayfromRESETdisabletoSENactive
Delayfrompower-upofAVDDandDRVDDtooutputstable
1022
40
msµsµsms
DESCRIPTION
MIN
TYP
MAX
UNIT
Power Supply(AVDD, DRVDD)t1 . 10 mst2 . 2 msRESET (Pin 35)t3 . 2 msSEN ActiveFigure2.ResetTimingDiagram
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ADS5520www.ti.com.......................................................................................................................................................SBAS310F–MAY2004–REVISEDOCTOBER2008
SERIALPROGRAMMINGINTERFACECHARACTERISTICS
TheADS5520hasathree-wireserialinterface.TheADS5520latchesserialdataSDATAonthefallingedgeofserialclockSCLKwhenSENisactive.
•SerialshiftofbitsisenabledwhenSENislow.SCLKshiftsserialdataatthefallingedge.•Minimumwidthofdatastreamforavalidloadingis16clocks.•Dataisloadedatevery16thSCLKfallingedgewhileSENislow.
•Incasethewordlengthexceedsamultipleof16bits,theexcessbitsareignored.•Datacanbeloadedinmultiplesof16-bitwordswithinasingleactiveSENpulse.
•Thefirst4-bitnibbleistheaddressoftheregisterwhilethelast12bitsaretheregistercontents.
SDATA
A3A2A1A0D11D10D9DATAD0ADDRESSMSB
Figure3.DATACommunicationis2-Byte,MSBFirst
tSLOADStWSCLKtWSCLKSCLK
tsu(D)SDATA
MSBth(D)LSB16xMSEN
tSLOADHtSCLKMSBLSBFigure4.SerialProgrammingInterfaceTimingDiagramTable2.SerialProgrammingInterfaceTimingCharacteristics
SYMBOLtSCLKtWSCLKtSLOADStSLOADHtDStDH
(1)
PARAMETERSCLKperiodSCLKdutycycleSENtoSCLKsetuptimeSCLKtoSENholdtime
DatasetuptimeDataholdtime
MIN(1)
5025%8686
50%
75%
nsnsnsns
TYP(1)
MAX(1)
UNITns
Typ,min,andmaxvaluesarecharacterized,butnotproductiontested.
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ADS5520SBAS310F–MAY2004–REVISEDOCTOBER2008.......................................................................................................................................................www.ti.com
Table3.SerialRegisterTable(1)
A3A2A1A0
D11
D10
D9
D8D7D6D5D4D3D2
D1DLLCTRL
11
11
00
11
00
00TP<1>
111111
111111
111111
000011
0000PDN01
00
00
00
00
00
00
00
00
00
XX
00
0011
00TP<0>0101
0000
0000
0000
0000
0000
0000
0000
XXXX
0000
00
00
00
00
00
00
00
01
00D0
ClockDLL
InternalDLLison;recommendedfor60MSPSto125MSPSclockspeeds.
InternalDLLisoff;recommendedfor2MSPSto80MSPSclockspeeds.TestMode
NormalmodeofoperationAlloutputsforcedto0Alloutputsforcedto1
Eachoutputbittogglesbetween0and1.PowerDown
Normalmodeofoperation
Deviceisputinpower-down(low-current)mode.
(2)(3)
DESCRIPTION
(1)(2)(3)
TheregistercontentsdefaulttotheappropriatesettingfornormaloperationuponRESET.
Thepatternsgivenareapplicabletothestraightoffsetbinaryoutputformat.If2'scomplementoutputformatisselected,thetestmodeoutputswillbethebinarytwo'scomplementequivalentofthesepatternsasdescribedintheOutputInformationsection.
Whileeachbittogglesbetween1and0inthismode,thereisnoassuredphaserelationshipbetweenthedatabitsD0throughD13.Forexample,whenD0isa1,D1innotassuredtobea0,andviceversa.
Table4.DataFormatSelect(DFS)Table
DFS-PINVOLTAGE(VDFS)VDFSt2 AVDD12DATAFORMATStraightBinary2'scomplementStraightBinary2'scomplementCLOCKOUTPUTPOLARITYDatavalidonrisingedgeDatavalidonrisingedgeDatavalidonfallingedgeDatavalidonfallingedge54 AVDDtVDFSt AVDD121287 AVDDtVDFSt AVDD1212VDFSu10 AVDD1210SubmitDocumentationFeedback
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