毕业设计(论文)外文资料翻译〔含原文〕

南 京 理 工 大 学

毕业设计(论文)外文资料翻译

教 学 点： 南京信息职业技术学院 专 业： 电子信息工程 姓 名： 陈洁 学 号： 4

外文出处： 《 Pci System Architecture 》

(用外文写)

附 件： 1.外文资料翻译译文；2.外文原文。 指导教师评语： 该生外文翻译没有基本的语法错误，用词准确，没有重要误译，忠实原文；译文通顺，条理清楚，数量与质量上达到了本科水平。 签名： 年 月 日 注：请将该封面与附件装订成册。

附件1：外文资料翻译译文

位PCI扩展

1. 位数据传送和位寻址：的能力

PCI规范给出了允许位总线主设备与位目标实现位数据传送的机理。在传送的开始，如果回应目标是一个位或32位设备，位总线设备会自动识别。如果它是位设备，达到8个字节（一个4字）可以在每个数据段中传送。假定是一串0等待状态数据段。在33MHz总线速率上可以每秒2兆字节获取（8字节／传送＊33百万传送字／秒），在66MHz总线上可以528M字节／秒获取。如果回应目标是32位设备，总线主设备会自动识别并且在下部4位数据通道上（AD[31::00]）引导，所以数据指向或来自目标。

规范也定义了位存储器寻址功能。此功能只用于寻址驻留在4GB地址边界以上的存储器目标。32位和位总线主设备都可以实现位寻址。此外，对位寻址反映的存储器目标（驻留在4GB地址边界上）可以看作32位或位目标来实现。

注意位寻址和位数据传送功能是两种特性，各自并且严格区分开来是非常重要的。一个设备可以支持一种、另一种、都支持或都不支持。 2. 位扩展信号

为了支持位数据传送功能，PCI总线另有39个引脚。

 REQ#被位总线主设备有效表明它想执行位数据传送操作。REQ#与FRAME#信号具有相同的时序和间隔。REQ#信号必须由系统主板上的上拉电阻来支持。当32位总线主设备进行传送时，REQ#不能又漂移。

 ACK#被目标有效以回应被主设备有效的REQ#（如果目标支持位数据传送），ACK#与DEVSEL#具有相同的时序和间隔（但是直到REQ#被主设备有效，ACK#才可被有效）。像REQ#一样，ACK#信号线也必须由系统主板上的上拉电阻来支持。当32位设备是传送目标时，ACK#不能漂移。

 AD[::32]包含上部4位地址／数据通道。  C/BE#[7::4]包含高4位命令/字节使能信号。

 PAR是为上部4个AD通道和上部4位C/BE信号线提供偶校验的奇偶校验位。 以下是几小结详细讨论位数据传送和寻址功能。 3. 在32位插入式连接器上的位卡

安装在32位扩展槽上的位卡只能自动地使用总线的下半部来执行传送，这是事实，因为系统主板的设计者将连接器上的REQ#输出引脚和ACK#输入引脚与系统主板上的上拉电阻分别连接而没有其它连接。

当位总线主设备安装在32位插槽并开始交易时，对于任何目标REQ#的有效是不可见的。此外，ACK#输出总被采样无效（因为它在系统主板上被上拉），这就迫使总线主设备在传送时只能使能总线下部分。而且，如果交易中被寻址的目标是位的，它会采样无效的REQ#（因为它在系统主板上被上拉），这就迫使目标在传送时只能利用总线下部分，并且使ACK#输出为不可用。

在自身卡上的位扩展信号线在它们使用时不能有漂移。如果插卡上的COMS输入接收器出现振动和泄露过量的电流，这就违反了规范的“绿色”原则。当插卡安装在32位槽时，它不能使用总线的上半部。插卡检测插槽的类型的方法（在启动开始时采样REQ#无效）下一节将描述。

4. 当未使用时，上拉可防止位扩展的漂移

在未使用时如果允许位扩展信号（AD[63::32]、C/BE[7::4]和PAR）漂移，那么插卡上的CMOS输入缓存器将振动并且泄漏过量电流。当不再使用时,为了防止扩展的漂移，要求系统主板设计者在扩展信号上加上拉电阻来防止漂移，因为这些上拉电阻可保证扩展位不漂移，嵌入在系统板上的位设备和安装在位PCI插入式连接器上的位卡，当它们不使用扩展位位时，不需要采取任何特殊措施防止扩展槽漂移。

位扩展在以下环境中不使用： 1．PCI总线空闲。

2．32位总线组设备正与一个32为目标进行交易。

3．32位总线主设备与一个位目标进行交易，当在交易的起始检测到REQ#无效时，目标不用总线的上半部。

4．位总线主设备寻址一个目标已进行32位数据传送（REQ#无效），并且目标驻留在低于4GB地址边界以下（在地址段和数据段不使用总线上半部）。不管目标是32位还是位，在数据中不使用总线的上半部（因为REQ#无效）。

5．一个位总线主设备试图与驻留在4GB边界以下的32位存储器目标进行传送时（REQ#无效）。在此情况下，主设备在地址段中只能使用总线的下半部分（因为它仅生成32位地址）。当它发现当前寻址的目标是32位目标时（当DEVSEL#无效时ACK#不能有效），主设备在数据段中停止使用总线的下半部。

4.1 32位PCI 连接器上的位插卡

位卡允许安装在32位卡插卡连接器上。连接器的主要部分（32位）包括所有32位PCI信号，同时连接器的扩展包含位信号（除了放置在连接器32位部分的REQ#和ACK#）.

当位设备安装在32位扩展槽上时，在AD[63::32]、C/BE[7::4]和PAR上的系统主板上拉对插入式卡是不可用的。这就意味着连接到扩展信号号上的插入式输入缓存器将会漂移，震动和泄漏电流。

规范中强调插入卡设计者不能通过在插入卡的扩展线上提供上拉电阻来解决这个问题，当卡安装在位扩展槽中用此方法会引起一些问题，在这些信号线上会需要2套上拉电阻（一套在插卡上，另一套在系统主板上）。如果所有设计者都用此方法，若共有多个位插卡的设备装入连接器上时，将会由多个上拉电阻在扩展信号线上，这就会造成上拉电阻过载。

规范中对一个位插卡给出了如何在起始时间确定是安装在了32位连接器上还是位连接器上的方法。如果插卡检测出被插入了位连接器上时，系统主板上的上拉电阻可在扩展信号不使用时防止卡上的输入接受不漂移；另一方面，如果位插卡检测出被插入32位卡连接器上时，卡上的逻辑可防止输入接收器的漂移，规范中列举了近似于以下几种方法：

 将输入缓存器关闭。

 不断的驱动输出（因为它们没有连接任何器件）。 4.2 位插卡如何确定所安装插槽的类型

当系统被加电时，复位信号会自动被有效。在此期间，系统主板上的逻辑必须有效REQ#、还有RST#。REQ#上面有一个上拉电阻与集成在系统主板上的所有位设备和所有位PCI扩展槽上的REQ#引脚相连。规范指出了每个32位PCI扩展槽上的REQ#信号线（REQ#和ACK#放置在连接器的32位部分），每一个都有自己的上拉电阻。

在复位期间，系统主板复位逻辑最初有效PCI RST#信号同时供电电源的POWERGOOD信号被无效。在RST#有效过程中，系统主板逻辑有效REQ#并保持有效直至它消除了RST#信号。在POWERGOOD被电源逻辑有效时，系统主板复位逻辑会无效PCI RST#信号。在RST#有效的尾部边沿，要求所有位设备采样REQ#信号的状态。

嵌入在系统主板或安装在位扩展槽上的所有位设备在RST#的尾沿采样REQ#

有效，这就要求它们镰刀系统主板上的扩展上拉电阻上并且当不使用它们时不需要采取特殊措施防止扩展信号漂移。

安装在32位插卡槽上的所有位设备，在RST#的尾部边沿都可检测到无效的REQ#，这就告知它们需要连接扩展信号上的系统主板的上拉电阻，插卡逻辑必须对本身的位卡上的扩展信号线的状态负责。所以插卡必须使用前一节提过的方法之一，防止卡的输入接受器泄漏过量电流。

附件2：外文原文

The -bit PCI Extension

The -bit PCI Extension

This chapter describes the -bit extension that permits masters and targets to perform eight byte transfers during each data phase. It also describes -bit addressing used to address memory targets that reside above the 4GB boundary.

1．-bit Ata Transfers and -bit Addressing: Seperate Capabilities

The PCI specification provides a mechanism that permits a -bit bus master to perform -bit data transfers with a -bit target. At the beginning of a transaction, the -bit bus maser automatically senses if the responding target is a -bit or a 32-bit device. If it’s a -bit device, up to eight bytes(a quadword) may be transferred during each data phase. Assuming a series of 0-wait state data phases, throughput of 2Mbytes/second can be achieved at a bus speed of 33MHz(8 bytes/transfer x 33 million transfers/second) and 528Mbytes/second at66MHz.If the responding target is a 32-bit device, the bus master automatically senses this and steers all data to or from the target over the lower four data paths(AD[31:0]).

The specification also defines -bit memory addressing capability. This capability is only used to address memory targets that reside above the 4GB address boundary. Both 32-and [bit bus masters can perform -bit addressing. In addition, memory target(that reside over the 4GB address boundary) that respond to -bit addressing can be implemented as either 32-or -bit targets.

2．-Bit Extension Signals

In order to support the -bit data transfer capability, the PCI bus implements an additional thirty-nine pins:

 REQ# is asserted by a -bit bus master to indicate that is would like to perform -bit data transfers.REQ# has the same timing and duration a s the FRAME# signal. The REQ# signal line must be supplied with a pull up resistor on the system board.REQ# cannot be permitted to float when a 32-bit bus master is performing a transaction.

 ACK# is asserted by a target in response to REQ# assertion by the master (if the target supports -bit data transfers).ACK# has the same timing and duration as DEVSEL#(but ACK# must not be asserted unless REQ# is asserted by the initiator).Like REQ#,the AcK# signal line must also be supplied with a pullup resistor on the system board.ACK# cannot be permitted to float when a 32-bit device si the target of transaction.

 AD [63::32] comprise the upper four address/data paths.

 C/BE# [7::4] comprise the upper four command/byte enable signals.

 PAR is the parity bit that provides even parity for the upper four AD paths and the upper four C/BE signal lines.

The following sections provide a detailed discussion of -bit data master and addressing capability.

3．-bit Cards in 32-bit Add-in Connectors

A -bit card installed in a 32-bit expansion slot automatically only uses the lower half of the bus to perform transfers. This is true because the system board designer connects the

REQ# output pin and the ACK# input pin on the connector to individual pull-ups on the system board and to nothing else.

When a -bit bus master is installed in a 32-bit card slot and it initiates a transaction, its assertion of REQ# is not visible to any of the target. In addition, its ACK# input is always sampled deasserted (because it’s pulled up on the system board).This forces the bus master to use only the lower part of the bus during the transfer. Furthermore, if the target addressed in the transaction is a -bit target, it samples REQ74# deasserted (because it’s pulled up on the system board),forcing it to only utilize the lower half of the bus during the transaction and to disable its ACK# output.

The -bit extension signal lines on the card itself cannot be permitted to float when they are not in use. The CMOS input receives on the card would oscillate and draw excessive current, thus violating the “green” aspect of the specification. hen the card is installed in a 32- bit slot, it cannot use the upper half of the bus. The manner in which the card detects the type of slot (REQ# sampled deasserted at startup time) is described in the next section.

4．Pullups Prevent -bit Extension from Floating When Not in Use

If the -bit extension signals (AD[63::32],C/BE[7::4]# and PAR are permitted to float when not in use, the CMOS input buffers on the card will oscillate and draw excessive current. In order to prevent the extension signals to keep them from floating. Because these pull-ups are guaranteed to keep the extension from floating when not in use, -bit devices that are embedded on the system board and -bit cards installed in -bit PCI add-in connectors don’t need to take any special action to keep the extension from floating when they are not using it.

The -bit extension is not in use under the following circumstance:

1. The PCI bus is idle.

2. A 32-bit bus master is performing a transaction with a 32-bit target.

3. A 32-bit bus master is performing a transaction with a -bit target. Upon detecting REQ# deasserted at the start of the transaction, the target will not use the upper half of the bus.

4. A -bit bus master addresses a target to perform 32-bit data transfers (REQ# deasserted) and the target resides below the 4GB boundary. In this case, the initiator only uses the lower half of the bus during the address phase(because it’s only generating a 32-bit address).When it discovers the currently-addressed target is a 32-bit target(ACK# not asserted when DEVSEL# asserted),the initiator ceases to use the upper half at the bus during the data phases.

4.1. a -bit Card in a 32-bit PCI Connector

Installation of a -bit card in a 32-bit card connector is permitted. The main(32-bit) portion of the connector contains all of the 32-bit PCI signals, which an extension to the connector contains the -bit extension signal(with the exception of REQ# and ACK# which are located on the 32-bit portion of the connector).

When a -bit device is installed in a 32-bit PCI expansion slot, the system board pull-ups on AD[63::32],C/BE#[7::4] and PAR are not available to the add-in card. This means that the add-in card’s input buffers that are connected to the extension signal pins will float, oscillate, and draw excessive current.

The specification states that the add-in card designer must not solve the problem by supplying pullup resistors on the extension lines on the add-in card. Using this approach would cause problems when the card is installed in a -bit expansion slot. There would then be tow

sets of pullup resistor on these signal line (the ones on the card plus the ones on the system board).If all designer solved the problem in this manner, a machine with multiple -bit cards inserted in -bit card connectors would have multiple pull-ups on the extension signal, resulting in pullup current overload.

The specification provides a method for a -b9it card to determine at startup time whether it’s installed in a 32-bit or a -bit connector. If the card detects that it is plugged into a -bit connector, the pull-ups on the system board will keep the input receives on the card from floating when the extension is not in use. On the other hand, if a y-bit card detects that it is a 32-bit card connector, the logic on the card must keep the input receives from switching. The specification states that an approach similar to one of the following should be use:

 Biasing the input buffer to turning it off.

 Actively driving the outputs continually (since they aren’t connected to anything). 4.2. How -bit Card Determines Type of Slot installed In

When the system is powered up, the reset signal is automatically asserted. During this period of time, the logic on the system board must assert the REQ# signal as well as RST#.REQ# has a single pullup resistor on it and is connected to the REQ# pin on all -bit devices integrated onto the system board and on all -bit PCI expansion slot. The specification states that the REQ# signal line on each 32-bit PCI expansion slot (REQ# and ACK# are located on the 32-bit portion of the connector), however, each has its own independent pullup resistor. During reset time, the system board reset logic initially asserts the PCI RST# signal while the POWERGOOD signal from the power supply is deasserted .During the assertion of RST# signal. When POWERGOOD is asserted by the power supply logic, the system board reset logic deasserts the PCI RST# signal. On the trailing-edge of RST# assertion, all -bit devices are required to sample the stated of the REQ# signal.

All -bit devices that are embedded on the system board or that they are installed in -bit expansion slots sample REQ# asserted on the trailing-edge of RST#. This informs them that they are connected to the extension pull-ups on the system board and need take no special action to keep the extension from floating when not using it.

All －bit devices that are installed in 32-bit card slot, however detect REQ# desserted on the trailing-edge of RST#. This informs them that they are not connected to the system board resident pull-ups on the extension signal. The card logic must therefore take responsibility for the state of its own on-card -bit extension signal lines. The card must therefore use one of the methods cited in the previous section to prevent excessive current draw by the card’s input receivers.