专利名称:Cell modeling in the design of an integrated
circuit
发明人:Attila Kovacs-Birkas申请号:US09878497申请日:20010611
公开号:US20020199155A1公开日:20021226
专利附图:
摘要:The invention relates to a method for modeling an input/output cell located onthe perimeter of an integrated circuit. A method is taught to model an the integratedcircuit when sufficient area is not available on the perimeter of the integrated circuit. The
input/output cell can be modeled in two locations; one location on the perimeter of thecell and a second location in the interior area, or core, of the integrated circuit. Themodel uses a cover to prevent the area of the core of the integrated circuit from beingused for other purposes. When the input/output cell is divided into a main cell and morethan one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timingof the signals to compensate for the input/output cell being divided into two areas. In anembodiment a software tool performs the functions of the model.
申请人:KOVACS-BIRKAS ATTILA
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