Literature Number: SPRU646A
January 2004
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Preface
Read This First
About This Manual
This document describes the interrupt selector, interrupt selector registers,and the available interrupts in the digital signal processors (DSPs) of theTMS320C6000 DSP family.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
-Registers in this document are shown in figures and described in tables.
J
Each register figure shows a rectangle divided into fields that representthe fields of the register. Each field is labeled with its bit name, itsbeginning and ending bit numbers above, and its read/write propertiesbelow. A legend explains the notation used for the properties.Reserved bits in a register figure designate a bit that is used for futuredevice expansion.
J
Related Documentation From Texas Instruments
The following documents describe the C6000 devices and related supporttools. Copies of these documents are available on the Internet at www.ti.com.Tip: Enter the literature number in the search box provided at www.ti.com.TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000 CPU architecture,instruction set, pipeline, and interrupts for these digital signal processors.TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000 DSPs.TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62x and TMS320C67x DSPs, develop-ment tools, and third-party support.
SPRU646A
Interrupt Selector and External Interrupts
3
TrademarksRelated Documentation From Texas Instruments/Trademarks
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64x DSP and discusses the application areas that areenhanced by the TMS320C64x VelociTI.TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for theTMS320C6000 DSPs and includes application program examples.TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studio integrated develop-ment environment and software tools.Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code ComposerStudio application programming interface (API), which allows you toprogram custom plug-ins for Code Composer.TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of theTMS320C6000 peripheral support library of functions and macros. Itlists functions and macros both by header file and alphabetically,provides a complete description of each, and gives code examples toshow how they are used.TMS320C6000 Chip Support Library API Reference Guide (literature
number SPRU401) describes a set of application programming interfaces(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks ofTexas Instruments.
4I nterrupt Selector and External InterruptsSPRU646A
Contents
Contents
12345
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Available Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7External Interrupt Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Configuring the Interrupt Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.1Interrupt Multiplexer High Register (MUXH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.2Interrupt Multiplexer Low Register (MUXL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.3External Interrupt Polarity Register (EXTPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPRU646AInterrupt Selector and External Interrupts5
Figures
Figures
1Interrupt Multiplexer High Register (MUXH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Interrupt Multiplexer Low Register (MUXL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
External Interrupt Polarity Register (EXTPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Tables
1Differences in C6000 DSP Interrupt Selectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72TMS320C620x/C670x DSP Available Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Interrupt Selector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Interrupt Multiplexer High Register (MUXH) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . 115Interrupt Multiplexer Low Register (MUXL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . 126TMS320C620x/C670x DSP Default Interrupt Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137External Interrupt Polarity Register (EXTPOL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . 148
Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6I nterrupt Selector and External InterruptsSPRU646A
Interrupt Selector and Exernal Interrupts
This document describes the interrupt selector, interrupt selector registers,and the available interrupts in the digital signal processors (DSPs) of theTMS320C6000 DSP family.
1Overview
The C6000 DSP peripheral set has up to 32 interrupt sources. The CPU how-ever has 12 interrupts available for use. The interrupt selector allows you tochoose and prioritize which 12 of the 32 your system needs to use. Theinterrupt selector also allows you to effectively change the polarity of externalinterrupt inputs.
Table 1 summarizes the differences between the interrupt selectors of theC6000 devices.
Table 1.
Features
Differences in C6000 DSP Interrupt Selectors
Supported on Device
C6000 devices have different available interrupts according to theirperipheral sets.C620x/C670x DSP only
All C6000 devices. On C64x DSP, these pins are MUXed with theGPIO peripheral pins.
Available InterruptsIACK and INUM pinsEXT_INT4−EXT_INT7 pins
2Available Interrupt Sources
Table 2 lists the available interrupts on the C620x/C670x DSP. See the device-specific datasheet for a list of the available interrupts on the C621x/C671x DSPand C64x DSP. For more information on interrupts, including the interruptvector table, see the TMS320C6000 CPU and Instruction Set ReferenceGuide (SPRU189).
SPRU646AInterrupt Selector and Exernal Interrupts7
Available Interrupt Sources
Table 2.TMS320C620x/C670x DSP Available Interrupts
Interrupt
Selection Number
00000b00001b00010b00011b00100b00101b00110b00111b01000b01001b01010b01011b01100b01101b01110b01111b10000b10001b
InterruptAcronymDSPINTTINT0TINT1SD_INTEXT_INT4EXT_INT5EXT_INT6EXT_INT7DMA_INT0DMA_INT1DMA_INT2DMA_INT3XINT0RINT0XINT1RINT1−XINT2†
PCI_WAKEUP‡
10010b
RINT2†ADMA_HLT‡
10011−11111b
†‡
Interrupt DescriptionHost port to DSP interruptTimer 0 interruptTimer 1 interrupt
EMIF SDRAM timer interruptExternal interrupt pin 4External interrupt pin 5External interrupt pin 6External interrupt pin 7DMA channel 0 interruptDMA channel 1 interruptDMA channel 2 interruptDMA channel 3 interruptMcBSP 0 transmit interruptMcBSP 0 receive interruptMcBSP 1 transmit interruptMcBSP 1 receive interruptReserved
McBSP 2 transmit interruptPCI wake up interruptMcBSP 2 receive interruptAuxiliary DMA halted interruptReserved
−
Only available on the C6202(B) DSP and C6203(B) DSPOnly available on the C6205 DSP
8Interrupt Selector and Exernal InterruptsSPRU646A
External Interrupt Signal TimingExternal Interrupt Signal Timing/Configuring the Interrupt Selector
3External Interrupt Signal Timing
EXT_INT4−EXT_INT7 and NMI are dedicated external interrupt sources
(EXT_INT4−EXT_INT7 pins are MUXed with the GPIO peripheral pins on theC64x DSP). In addition, the receive frame synchronization (FSR) and transmitframe synchronization (FSX) signals of the multichannel buffered serial port(McBSP) can be programmed to directly drive the RINT and XINT signals.Because these signals are asynchronous, they are synchronized before beingsent to either the DMA/EDMA or CPU. Refer to the TMS320C6000 CPU andInstruction Set Reference Guide (SPRU189) and your device-specificdatasheet for details on external interrupt signals timing.
For the C620x/C670x DSP, the NMI can interrupt a maskable interrupt fetchpacket (ISFP) just before the interrupt reaches E1. In this case, an IACK andINUM for the NMI is not seen because the IACK and INUM corresponding tothe maskable interrupt is on the pins.Note:
The IACK and INUM pins do not exist on the C621x/C671x DSP andC64x DSP. These pins only exist on the C620x/C670x DSP.
4Configuring the Interrupt Selector
The interrupt selector registers are meant to be configured once after resetduring initialization and before enabling interrupts.Note:
After the registers have been set, the interrupt flag register should be clearedto remove any spurious transitions caused by the configuration.
You may reconfigure the interrupt selector during other times, but spuriousinterrupt conditions may be detected by the CPU on the interrupts affected bythe modified fields. For example, if EXT_INT4 is low, EXT_INT5 is high, andINT9 is remapped from EXT_INT4 to EXT_INT5, the low-to-high transition onINT9 is recognized as an interrupt and sets IF9.
SPRU646AInterrupt Selector and Exernal Interrupts9
Registers
5Registers
Table 3 shows the interrupt selector registers. The interrupt multiplexer registersdetermine the mapping between the interrupt sources described in section 2and the CPU interrupts 4 through 15 (INT4−INT15). The external interruptpolarity register sets the polarity of external interrupts. See the device-specificdatasheet for the memory address of these registers.
Table 3.
AcronymMUXHMUXLEXTPOL
Interrupt Selector Registers
Register Name
Interrupt multiplexer high registerInterrupt multiplexer low registerExternal interrupt polarity register
Section5.15.25.3
5.1Interrupt Multiplexer High Register (MUXH)
The interrupt multiplexer high register (MUXH) maps the interrupt sources toparticular interrupts. The MUXH is shown in Figure 1 and described in Table 4.The INTSEL10−INTSEL15 fields correspond to the CPU interruptsINT10−INT15. By setting the INTSEL bits to the value of the desired interruptselection number, you can map any interrupt source to any CPU interrupt. Thedefault values of the INTSEL bits are shown in Figure 1. The default mappingof interrupt sources to CPU interrupts for the C620x/C670x devices are shownin Table 6 (page 13). For the default mapping of interrupt sources to CPUinterrupts for the C621x/C671x and C64x devices, see the device-specificdatasheet.
5.2Interrupt Multiplexer Low Register (MUXL)
The interrupt multiplexer low register (MUXL) maps the interrupt sources toparticular interrupts. The MUXL is shown in Figure 2 and described in Table 5.The INTSEL4−INTSEL9 fields correspond to the CPU interrupts INT4−INT9.By setting the INTSEL bits to the value of the desired interrupt selectionnumber, you can map any interrupt source to any CPU interrupt. The defaultvalues of the INTSEL bits are shown in Figure 2. The default mapping ofinterrupt sources to CPU interrupts for the C620x/C670x devices are shownin Table 6 (page 13). For the default mapping of interrupt sources to CPUinterrupts for the C621x/C671x and C64x devices, see the device-specificdatasheet.
10Interrupt Selector and Exernal InterruptsSPRU646A
Registers
Figure 1.
31ReservedR-015ReservedR-0
1430
Interrupt Multiplexer High Register (MUXH)
2625
INTSEL15R/W-00010
109
INTSEL12R/W-01011
INTSEL11R/W-01010INTSEL14R/W-00001
54
INTSEL10R/W-00011
2120
INTSEL13R/W-00000
016
Legend:R = Read only; R/W = Read/Write; -n = value after reset
Table 4.
Bit3130−2625−2120−161514−109−54−0
†
Interrupt Multiplexer High Register (MUXH) Field Descriptions
field†ReservedINTSEL15INTSEL14INTSEL13ReservedINTSEL12INTSEL11INTSEL10
symval†−OF(value)OF(value)OF(value)−OF(value)OF(value)OF(value)
Value0
Description
Reserved. The reserved bit location is always read as 0. Avalue written to this field has no effect.
0−1FhInterrupt selector 15 bits. This value maps interrupt 15 to any
CPU interrupt.0−1FhInterrupt selector 14 bits. This value maps interrupt 14 to any
CPU interrupt.0−1FhInterrupt selector 13 bits. This value maps interrupt 13 to any
CPU interrupt.0
Reserved. The reserved bit location is always read as 0. Avalue written to this field has no effect.
0−1FhInterrupt selector 12 bits. This value maps interrupt 12 to any
CPU interrupt.0−1FhInterrupt selector 11 bits. This value maps interrupt 11 to any
CPU interrupt.0−1FhInterrupt selector 10 bits. This value maps interrupt 10 to any
CPU interrupt.
For CSL implementation, use the notation IRQ_MUXH_INTSELn_symval
SPRU646AInterrupt Selector and Exernal Interrupts11
Registers
Figure 2.
31ReservedR-015ReservedR-0
1430
Interrupt Multiplexer Low Register (MUXL)
2625
INTSEL9R/W-01001
109
INTSEL6R/W-00110
INTSEL5R/W-00101INTSEL8R/W-01000
54
INTSEL4R/W-00100
2120
INTSEL7R/W-00111
016
Legend:R = Read only; R/W = Read/Write; -n = value after reset
Table 5.
Bit3130−2625−2120−161514−109−54−0
†
Interrupt Multiplexer Low Register (MUXL) Field Descriptions
field†ReservedINTSEL9INTSEL8INTSEL7ReservedINTSEL6INTSEL5INTSEL4
symval†−OF(value)OF(value)OF(value)−OF(value)OF(value)OF(value)
Value0
Description
Reserved. The reserved bit location is always read as 0. Avalue written to this field has no effect.
0−1FhInterrupt selector 9 bits. This value maps interrupt 9 to any
CPU interrupt.0−1FhInterrupt selector 8 bits. This value maps interrupt 8 to any
CPU interrupt.0−1FhInterrupt selector 7 bits. This value maps interrupt 7 to any
CPU interrupt.0
Reserved. The reserved bit location is always read as 0. Avalue written to this field has no effect.
0−1FhInterrupt selector 6 bits. This value maps interrupt 6 to any
CPU interrupt.0−1FhInterrupt selector 5 bits. This value maps interrupt 5 to any
CPU interrupt.0−1FhInterrupt selector 4 bits. This value maps interrupt 4 to any
CPU interrupt.
For CSL implementation, use the notation IRQ_MUXL_INTSELn_symval
12Interrupt Selector and Exernal InterruptsSPRU646A
Registers
Table 6.
TMS320C620x/C670x DSP Default Interrupt Mapping
CPU Related
INTSEL InterruptInterruptINTSEL fieldReset ValueAcronymInterrupt DescriptionINT4INTSEL400100bEXT_INT4External interrupt pin 4INT5INTSEL500101bEXT_INT5External interrupt pin 5INT6INTSEL600110bEXT_INT6External interrupt pin 6INT7INTSEL700111bEXT_INT7External interrupt pin 7INT8INTSEL801000bDMA_INT0DMA Channel 0 InterruptINT9INTSEL901001bDMA_INT1DMA Channel 1 interruptINT10INTSEL1000011bSD_INTEMIF SDRAM timer interruptINT11INTSEL1101010bDMA_INT2DMA Channel 2 interruptINT12INTSEL1201011bDMA_INT3DMA Channel 3 interruptINT13INTSEL1300000bDSPINTHost port to DSP interruptINT14INTSEL1400001bTINT0Timer 0 interruptINT15
INTSEL15
00010b
TINT1
Timer 1 interrupt
SPRU646AInterrupt Selector and Exernal Interrupts13
Registers
5.3External Interrupt Polarity Register (EXTPOL)
The external interrupt polarity register (EXTPOL) allows you to change thepolarity of the four external interrupts (EXT_INT4−EXT_INT7). The EXTPOLis shown in Figure 3 and described in Table 7. When the XIP bit is its defaultvalue of 0, a low-to-high transition on an interrupt source is recognized as aninterrupt. By setting the corresponding XIP bit to 1, you can invert the externalinterrupt source and effectively have the CPU detect high-to-low transitions ofthe external interrupt. Changing an XIP bit value creates transitions on therelated CPU interrupt (INT4−INT7) that the external interrupt (EXT_INT) isselected to drive. For example, if XIP4 is changed from 0 to 1 and EXT_INT4is low or if XIP4 is changed from 1 to 0 and EXT_INT4 is high, the CPU interruptthat is mapped to EXT_INT4 becomes set. EXTPOL only affects interrupts tothe CPU and has no effect on DMA events.
Figure 3.
31
External Interrupt Polarity Register (EXTPOL)
8
ReservedR-0
7
ReservedR-0
43XIP7R/W-0
2XIP6R/W-0
1XIP5R/W-0
0XIP4R/W-0
Legend:R = Read only; R/W = Read/Write; -n = value after reset
Table 7.
Bit31−43−0
External Interrupt Polarity Register (EXTPOL) Field Descriptions
FieldReservedXIP
symval†−OF(value)
Value00−Fh
Description
Reserved. The reserved bit location is always read as 0. A valuewritten to this field has no effect.
External interrupt polarity bits. A 4-bit unsigned value used tochange the polarity of the four external interrupts (EXT_INT4 toEXT_INT7).
A low-to-high transition on an interrupt source is recognized as aninterrupt.
A high-to-low transition on an interrupt source is recognized as aninterrupt.
01
†
For CSL implementation, use the notation IRQ_EXTPOL_XIP_symval
14Interrupt Selector and Exernal InterruptsSPRU646A
Revision History
Table 8 lists the changes made since the previous version of this document.
Table 8.
Page791010
Document Revision History
Additions/Modifications/Deletions
Changed second sentence in Section 2: See the device-specific datasheet for a list of the avail-able interrupts on the C621x/C671x DSP and C64x DSP.Deleted Table 3, TMS320C621x/C671x DSP Available Interrupts.
Deleted Table 4, TMS320C64x DSP Available Interrupts. Subsequent tables renumbered.Changed last two sentences in Section 5.1: By setting the INTSEL bits to the value of the desiredinterrupt selection number, you can map any interrupt source to any CPU interrupt. The defaultvalues of the INTSEL bits are shown in Figure 1. The default mapping of interrupt sources to CPUinterrupts for the C620x/C670x devices are shown in Table 6 (page 13). For the default mapping ofinterrupt sources to CPU interrupts for the C621x/C671x and C64x devices, see thedevice-specific datasheet.
Changed last two sentence in Section 5.2: By setting the INTSEL bits to the value of the desiredinterrupt selection number, you can map any interrupt source to any CPU interrupt. The defaultvalues of the INTSEL bits are shown in Figure 2. The default mapping of interrupt sources to CPUinterrupts for the C620x/C670x devices are shown in Table 6 (page 13). For the default mapping ofinterrupt sources to CPU interrupts for the C621x/C671x and C64x devices, see thedevice-specific datasheet.
Changed Table 6 to TMS320C620x/C670x DSP only.
10
13
SPRU646AInterrupt Selector and External Interrupts15
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16Interrupt Selector and External InterruptsSPRU646A
Index
Index
Aavailable interruptsC620x DSP8C670x DSP8
INTSEL15 bits
11
MMUXH10MUXL10
Cconfiguration of the interrupt selector
9
Nnotational conventions
3
Ddefault interrupt mappingC620x DSP13C670x DSP13
Ooverview
7
Eexternal interrupt polarity register (EXTPOL)EXTPOL14
14
Rregisters10
external interrupt polarity register (EXTPOL)14interrupt multiplexer high register (MUXH)10interrupt multiplexer low register (MUXL)10related documentation from Texas Instruments3revision history15
Iinterrupt multiplexer high register (MUXH)10interrupt multiplexer low register (MUXL)10INTSEL4 bits12INTSEL5 bits12INTSEL6 bits12INTSEL7 bits12INTSEL8 bits12INTSEL9 bits12INTSEL10 bits11INTSEL11 bits11INTSEL12 bits11INTSEL13 bits11INTSEL14 bits11SPRU646A
Ssignal timing interrupt9sources of interrupts7
Ttrademarks
4
XXIP bits
14
17
Interrupt Selector and External Interrupts
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