Pin Definitions
Table1-5 lists the pin definitions used in UltraScale and UltraScale+ device packages.
Table 1-5:
Pin Definitions
Type
Direction
Description
Pin NameUser I/O Pins
IO_L[1to24][PorN]_T[0to3] [UorL]_N[0to12]_ [multi-function]_[bank number] orIO_T[0to3][UorL]_N[0to12]_[multi-function]_[bank number]
Most user I/O pins are capable of differential signaling and can be implemented as pairs. Each user I/O pin name consists of several indicator labels, where:•IO indicates a user I/O pin.
•L[1to24] indicates a unique differential pair with P(positive) and N (negative) sides. User I/O pins withoutthe L indicator are single-ended.
Dedicated
Input/Output
•T[0 to 3][U or L] indicates the assigned byte group andnibble location (upper or lower portion) within thatgroup for the pin.•N[0 to 12] the number of the I/O within its byte group.•[multi-function] indicates any other functions that thepin can provide. If not used for this function, the pin canbe a user I/O.•[bank number] indicates the assigned bank for the userI/O pin.
User I/O Multi-Function Pins
Four global clock (GC) pin pairs are in each bank. HDGC pins have direct access to the global clock buffers. GC pins have direct access to the global clock buffers, MMCMs, and PLLs that are in the clock management tile (CMT) adjacent to the same I/O bank. GC and HDGC inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC and HDGC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is
imperative. GC or HDGC pins can be treated as user I/O when not used as input clocks.
Up-to-date information about designing with the GC (or HDGC) pin is available in the UltraScale Architecture Clocking Resources User Guide (UG572) [Ref6].This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with a reference resistor).
GC or HDGC
Multi-functionInput/Output
VRP(1)
Multi-function
N/A
UltraScale Device Packaging and PinoutsUG575 (v1.14) March 18, 2020
Chapter 1:Packaging Overview
UltraScale Device Packaging and PinoutsUG575 (v1.14) March 18, 2020
Chapter 1:Packaging Overview
UltraScale Device Packaging and PinoutsUG575 (v1.14) March 18, 2020
Chapter 1:Packaging Overview
Die Level Bank Numbering Overview
Banking and Clocking Summary
•
For each device, not all banks are bonded out in every package.
GTH/GTY/GTM Columns
••••
One GTH/GTY Quad=Four transceivers=Four GTHE3 or GTYE3 primitives.One GTM Dual=Two transceivers=Two GTME3 primitivesNot all GT Quads/Duals are bonded out in every package.
Also shown are quads/duals labeled with RCAL. This specifies the location of the RCALmasters for each device. With respect to the package, the RCAL masters are located onthe same package pin for each package, regardless of the device.
The XY coordinates shown in each quad/dual correspond to the transceiver channelnumber found in the pin names for that quad/dual, as shown in Figure1-1.
An alphabetic designator is shown in each quad/dual. Each letter corresponds to thecolumns in Table1-7 and Table1-9.
The power supply group is shown in brackets [] for each quad/dual.
•••
I/O Banks
•
Each user I/O bank has a total of 52 I/Os where 48 can be used as differential(24differential pairs) or single-ended I/Os. The remaining four function only assingle-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled aspartial.
Adjacent to each bank is a physical layer (PHY) containing a CMT and other clockresources.
Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.Banks are arranged in columns and separated into rows which are pitch-matched withadjacent PHY, clock regions, and GT blocks.
An alphabetic designator is shown in each bank. Each letter corresponds to thecolumns in Table1-7 and Table1-9.
•••••
UltraScale Device Packaging and PinoutsUG575 (v1.14) March 18, 2020
Chapter 1:Packaging Overview
UltraScale Device Packaging and PinoutsUG575 (v1.14) March 18, 2020
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