MD1210 Initial Release High Speed, Dual MOSFET Driver Features General Description The Supertex MD1210 is a high speed, dual MOSFET driver. It is designed to drive high voltage N- and P-channel MOSFET transistors for medical ultrasound applications and other application requiring a high output current for a capacitive load. The high-speed input stage of the MD1210 can operate from 1.2 to 5.0 volt logic interface with an optimum operating input signal range of 1.8 to 3.3 volts. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1210 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5.0 and –5.0 volts, and the output L and H levels may be varied anywhere over the range of –5.0 to +5.0 volts. The output stage is capable of peak currents of up to ±2.0 amps, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A output high and the B output low. This assists in properly pre-charging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. 6.0ns rise and fall time with 1000pF load 2.0A peak output source/sink current 1.2V to 5V input CMOS compatible 4.5V to 13V total supply voltage Smart Logic threshold Low jitter design Dual matched channels Outputs can swing below ground Low inductance package Thermally-enhanced package Applications Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation PIN diode driver Clock driver/buffer High speed level translator Typical Application Circuit NR0131051PR120104 MD1210 Ordering Information Package Option 12-lead 4x4x0.9 QFN MD1210 MD1210K6 Device Product Marking Information 1 line 1210 Device Number nd2 line YWLL Year, Week Code, Lot Number Example: 5A88 means Lot #88 of first or second week in 2005 stAbsolute Maximum Ratings* VDD-VSS, Logic Supply Voltage VH, Output High Supply Voltage VL, Output Low Supply Voltage VSS, Low Side Supply Voltage Logic Input Levels Maximum Junction Temperature Storage Temperature -0.5V to +13.5VVL-0.5V to VDD+0.5VVSS-0.5V to VH+0.5V-7.0V to +0.5VVSS-0.5V to VSS+7.0V+125°C-65°C to 150°C Pin1→ 1210 YWLL Top View *Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. DC Electrical Characteristics (Over operating conditions unless otherwise specified, VH=VDD1=VDD2=12V, VL=VSS1=VSS2=0V, VOE=3.3V, TJ= 25°C) Sym Parameter VDD-VSS Logic supply voltage VSS VH VL IDD1Q IDD2Q IHQ IDD1 IDD2 IH VIH VIL IIH IIL VIH VIL RIN CIN θJA θJC Min Typ Max Units4.5 13 V -5.5 VSS 0 1.2 0 0.55 0.88 6.6 23 0 V Conditions Low side supply voltage Output high supply voltage Output low supply voltage VDD1 quiescent current VDD2 quiescent current VH quiescent current VDD1 average current VDD2 average current VH average current Input logic voltage high Input logic voltage low Input logic current high Input logic current low OE Input logic voltage high OE Input logic voltage low Input logic impedance to GND Logic input capacitance Thermal resistance to air Thermal resistance to case HDDVSS+2.0 VDD V VDD-2 V 10 10 0.3 1.0 1.0 5.0 0.3 mA µA µA mA mA mA V µA µA V V For logic input OE One channel on at 5.0Mhz, No load No input transitions VOE-0.3 5.0 V For logic inputs INA and INB. 12 20 30 KΩ 5.0 47 7.0 10 All Inputs 1oz. 4-layer 3x4inch PCB with thermal °C/W pad and thermal via array. °C/W pF Outputs (V=VRSOURCE ISINK ISOURCE 1=VDD2=12V, VL=VSS1=VSS2=0V, VOE=3.3V, TJ=25°C) Sym Parameter RSINK Output sink resistance Output source resistance Peak output sink current Peak output source current Min Typ Max Units 12.5 Ω 2.0 2.0 12.5 Ω A A Conditions ISINK =50mA ISOURCE =50mA 2NR013105 MD1210 AC Electrical Characteristics (V=VHDD1=VDD2=12V, VL=VSS1=VSS2=0V, VOE=3.3V, TJ=25°C) Sym Parameter tirf tPLH tPHL tPOE tr tf l tr - tf l l tPLH-tPHL l ∆tdm Inputs or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low Propagation delay OE to outputs Output rise time Output fall time Rise and fall time matching Propagation low to high and high to low matching Propagation delay Match Min Typ Max Units Conditions 10 ns Logic input edge speed requirement 7.0 ns No load, see timing diagram 7.0 ns Input signal rise/fall time 2ns 9.0 ns 6.0 6.0 1.0 TBD ns ns ns CLOAD=1000pF, see timing diagram Input signal rise/fall time 2ns 1.0 ns ±2.0 TBD ns Device to device delay match Logic Truth Table Logic Inputs Output OE INA INB OUTA OUTB H L L VH VH H L H VH VL H H L VL VH H H H VL VL L X X VH VL Timing Diagram 3.3V50%0V50%Propagation Delay IN OUT tPLH90%10%tPHL90%10%0VtrtfSimplified Block Diagram Logic Input Threshold 3NR013105 Detailed Block Diagram VDD1VDD2VHMD1210 OELevelShifterLevelShifterOUTAINA Level INBShifter GND Application Information VSS2VLVHVDD2OUTBSUBVSS1VSS2VLFor proper operation of the MD1210, low inductance bypass capacitors should be used on the various supply pins. The GND input pin should be connected to the digital ground. The INA, INB, and OE pins should be connected to their logic source with a swing of GND to logic level high which is 1.2 to 5.0 volts. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1210 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS1, VSS2, and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connections VDD1 and VDD2 should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. A common capacitor and voltage source may be used for these two pins, which should always have the same DC voltage applied. For applications sensitive to jitter and noise, separate decoupling networks may be used for VDD1 and VDD2. The supplied voltages of VH and VL determine the output logic levels. These two pins can draw fast transient currents of up to 2.0A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0µF may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistor in series with the output signal to obtain better waveform integrity at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention to the parasitic coupling from the driver output to the input signal terminals. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that the circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. 4NR013105 MD1210 Pin Description VDD1 VDD2 VSS1 VSS2 VH VL GND OE INA INB High side analog circuit and level shifter supply voltage. Should be at the same potential as VDD2. High side gate drive supply voltage Low side analog circuit and level shifter supply voltage. Should be at the same potential as VSS2. Low side gate drive supply voltage Supply voltage for P-channel output stage Supply voltage for N-channel output stage Logic input ground reference Output-enable logic input. When OE is high, (VOE+VGND)/2 sets the threshold transition between logic level high and low for INA and INB. When OE is low, OUTA is at VH and OUTB is at VL regardless of INA and INB. Logic input. Controls OUTA when OE is high. Input logic high will cause the output to swing to VL. Input logic low will cause the output to swing to VH. Logic input. Controls OUTB when OE is high. Input logic high will cause the output to swing to VL. Input logic low will cause the output to swing to VH. Output driver. Swings from VH to VL. Intended to drive the gate of an external P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external P-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an external N-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external N-channel MOSFET. OUTA OUTB Pin Configuration Pin # Function 122.15101 INA 2 VL 3 INB 4 GND 5 VSS1 6 VSS2 7 OUTB 8 VH 9 OUTA 10 VDD2 11 VDD1 12 OE Note Thermal Pad, and substrate are connected to Pin#5,VSS1 0.30319QFN-124x4x0.972.150.50.806 (TopView,mm)Doc.#: DSFP-MD1210 NR013105 5NR013105
